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# Zynq carrier for RFoWR based application (CITY)
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# Zynq CarrIer for RFoWR based application (CITY)
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## Project description
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This board, based on the [FASEC Zynq SoC design](/projects/fasec/wikis/home) , is intended to be used for application requiring signals synchronized to an RF master source distribution over a [White Rabbit network](https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo).
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It mainly provides:
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- WR connectivity
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This card can be used to distribute RF signals over a [White Rabbit network](https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo).
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This board has been developed in order to be used for the ESRF accelerators timing system:
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- Bunch injection/extraction, Storage Ring filling
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- Beam synchronous triggers for accelerators diagnostic and beamlines experiments
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CITY is based on two main design:
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- [FASEC Zynq SoC design](https://www.ohwr.org/project/fasec/wikis/home)
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- RFoWR: based on [FMC DAC 12b 1cha DDS](https://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/wikis)
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- 12 TTL outputs (6 of them have fine delay unit and RF resynchronization)
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- 4 TTL inputs
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- 2 FMC slots
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**Below is only a template.
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Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)**
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*SPEC 1.1 first prototype**
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## Main Features
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- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
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anymore*
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
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- special versions with XC6SLX100T and XC6SLX150T available
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- FMC slot with low pin count (LPC) connector
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- Vadj fixed to 2.5V
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG, I2C
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- Stand-alone features
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- External 12V power supply connector
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Power consumption: 5-12 Watt, depending on application
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- Optimised for cost
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- 6-layer PCB
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- Optional cooling [fan](Fan-Design) for the mezzanine.
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It is a standalone pizza-box module, enclosed in a 19"1U rack.
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## Main features
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- XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e.
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Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called
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PS, i.e. Processing System)
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- 2x Low-Pin Count FMC slots
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- FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1
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GTP transceiver with clock, 2 clock pairs, JTAG, I2C
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- FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs,
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JTAG, I2C
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- FPGA configuration
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- From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD
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card
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- Clocking resources
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- 1x 33.33 MHz fixed oscillator, SoC main clock (clock
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distribution to PL possible)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 1x ~10-800MHz Programmable VCXO (Si571, custom part: 352MHz center frequency)
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- 1x AD9516 frequency synthesizer/fanout: WR domain
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- 1x AD9510 frequency synthesizer/fanout: RF domain
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- On-board memories
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- 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)
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- 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel &
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root file system storage (S25FL128SAGMFIR01)
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- Miscellaneous
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- UCD90120ARGC power controller (programmable over JTAG) to survey
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power rails and manage power-on and power-off sequence
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- Xilinx-style JTAG connector
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- Front panel
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- 1x SMA for RF input (mode master)
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- 1x SMA for RF output (synthesized, slave mode)
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- 1x SMA for user clock output (WR/RF clock multiplexed)
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- 4x LEMO-00 digital input (optional 50 Ohm termination, configurable input voltage threshold)
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- 12x LEMO-00 digital outputs (6 of them have fine delay tuning + RF resynchronization)
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- 1x programmable LED (module status)
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- Back panel
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- 1x LEMO connector for WR PPS output
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- 1x BNC connector for WR 10MHz output
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- 1x RJ45 port for 10/100/1000 Mbit Ethernet
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- 1x Micro-USB connector (FT232) for UART console
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- 1x Push button for POR Reset
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- 1x SFP port for WR link
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- 1x SATA connector for GTX user port
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- 10-layer PCB
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-----
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## Project information
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- Official production documentation: [EDMS EDA-02189](http://edms.cern.ch/nav/eda-02189)
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- [Users](Users)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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- Licenced under [CERN OHL V1.2](https://www.ohwr.org/project/cernohl/wikis/Documents/CERN-OHL-version-1.2)
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| ... | ... | @@ -68,9 +116,9 @@ Please update using the [recommended setup and usage guide](https://www.ohwr.org |
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| Date | Event |
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| --------- | ------ |
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| 12-09-2019| Start working on project. Collecting main specifications.|
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| 12-09-2019| ohwr pages started. |
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| 10-09-2019| Launch manufacturing of 2 board prototypes. |
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| 12-09-2019| ohwr pages started. |
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-----
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12 September 2019 |
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\ No newline at end of file |
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13 September 2019 |
