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- [FASEC Zynq SoC design](https://www.ohwr.org/project/fasec/wikis/home)
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- [FMC DAC 12b 1cha DDS](https://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/wikis)
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It is a standalone pizza-box module, enclosed in a 19"1U rack.
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It is a standalone module enclosed in a 19"1U rack.
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Below is an image of the PCB top view:
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## Main features
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- XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e.
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| ... | ... | @@ -56,22 +53,23 @@ Below is an image of the PCB top view: |
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- Front panel
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- 1x SMA for RF input (mode master)
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- 1x SMA for RF output (synthesized, slave mode)
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- 1x SMA for user clock output (WR/RF clock multiplexed)
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- 1x SMA for user clock output (DDS|[WR|RF]/N clock multiplexed)
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- 4x LEMO-00 digital input (optional 50 Ohm termination, configurable input voltage threshold)
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- 12x LEMO-00 digital outputs (6 of them have fine delay tuning + RF resynchronization)
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- 12x LEMO-00 digital outputs (6 of them have fine delay tuning @10ps steps)
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- 1x programmable LED (module status)
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- 2x LED for WR & RF valid status
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- Back panel
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- 1x LEMO connector for WR PPS output
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- 1x BNC connector for WR 10MHz output
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- 1x RJ45 port for 10/100/1000 Mbit Ethernet
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- 1x RJ45 port for 10/100/1000 Mbps Ethernet
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- 1x Micro-USB connector (FT232) for UART console
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- 1x Push button for POR Reset
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- 1x SFP port for WR link
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- 1x SATA connector for GTX user port
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- 1x SFP port for GTX user port
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- 10-layer PCB
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## Prototypes
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The board prototypes have been received and tested. Issues encountered have been created in Issues category of this repository.
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## Prototypes test
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February 2020: the board prototypes have been tested and debugged. Issues encountered have been created in Issues category of this repository.
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Main features tested:
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- Power supplies
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- Zynq PS (baremetal, Linux)
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- RFoWR synchronization in both Master & Slave modes with a 352MHz reference input frequency.
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- Outputs stages (TTL basic and fine-delayed, RF reconstructed, PPS, 10MHz...)
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## Releases
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### PCB project
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* V2: [CITY-V2-0.tar.gz](uploads/8bd333f3737d91af33c07c17e54e6cef/CITY-V2-0.tar.gz)
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### Enclosure mechanics
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To be added.
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### Gateware
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See in this repository. Not yet available.
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-----
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## Project information
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| ... | ... | @@ -111,7 +119,9 @@ Main features tested: |
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| --------- | ------ |
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| 10-09-2019| Launch manufacturing of 2 board prototypes. |
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| 12-09-2019| ohwr pages started. |
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| 17-03-2020| CITY prototypes received and tested. V2 ready. |
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| 17-03-2020| CITY prototypes tested and debugged. V2 ready. |
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| 15-10-2020| 4 boards CITY V2 received. |
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| 08-04-2021| CITY V2 minor fix applied and released. Manufacturing files setup on going (assembly, configuration and tests procedures, mechanics, PCB, cabling schema, etc...). Prepare small batch (10 units) order. |
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-----
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| ... | ... | |
