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# Zynq carrier for RFoWR based application (CITY)
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## Project description
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This board, based on the [FASEC Zynq SoC design](/projects/fasec/wikis/home) , is intended to be used for application requiring signals synchronized to an RF master source distribution over a [White Rabbit network](https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo).
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It mainly provides:
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- WR connectivity
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- RFoWR: based on [FMC DAC 12b 1cha DDS](https://ohwr.org/project/fmc-dac-600m-12b-1cha-dds/wikis)
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- 12 TTL outputs (6 of them have fine delay unit and RF resynchronization)
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- 4 TTL inputs
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- 2 FMC slots
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**Below is only a template.
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Please update using the [recommended setup and usage guide](https://www.ohwr.org/project/ohr-support/wikis/Administrator-guide#recommended-setup-usage)**
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*SPEC 1.1 first prototype**
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## Main Features
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- 4-lane PCIe (Gennum GN4124) *obsolete component, not available
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anymore*
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
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- special versions with XC6SLX100T and XC6SLX150T available
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- FMC slot with low pin count (LPC) connector
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- Vadj fixed to 2.5V
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG, I2C
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- No dedicated clock signals from Carrier to FMC (only available
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on HPC pins)
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- Stand-alone features
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- External 12V power supply connector
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- mini USB connector
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- 4 LEDs
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- 2 buttons
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- Power consumption: 5-12 Watt, depending on application
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- Optimised for cost
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- 6-layer PCB
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- Optional cooling [fan](Fan-Design) for the mezzanine.
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-----
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## Project information
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- Official production documentation: [EDMS EDA-02189](http://edms.cern.ch/nav/eda-02189)
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- [Users](Users)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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- Licenced under [CERN OHL V1.2](https://www.ohwr.org/project/cernohl/wikis/Documents/CERN-OHL-version-1.2)
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-----
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## Contacts
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### Commercial producers
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- not commercially available yet
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### General questions about project
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- [Antonin Broquet](mailto:antonin.broquet@esrf.fr) - ESRF
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-----
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## Status
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| Date | Event |
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| --------- | ------ |
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| 12-09-2019| Start working on project. Collecting main specifications.|
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| 12-09-2019| ohwr pages started. |
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-----
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12 September 2019 |
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\ No newline at end of file |
