Commit 428a9d35 authored by Adrian Byszuk's avatar Adrian Byszuk

Fix PCIe PIPE mode simulation

parent c412a235
......@@ -1940,7 +1940,7 @@ begin
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN,
PCIE_EXT_CLK => "FALSE",
PIPE_SIM_MODE => "FALSE"
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--------------------------------------------------------------------------------------------------------------------
......
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