Switch to simulation with Modelsim/Questa. ISim is so buggy that it doesn't work either way.

c412a235 · Adrian Byszuk · c5c76105 · c412a235 · c412a235 · c412a235
Commit c412a235 authored Mar 06, 2013 by Adrian Byszuk
Showing with 1065 additions and 254 deletions

Makefile hdl/testbench/pcie/Makefile +192 -250

Manifest.py hdl/testbench/pcie/Manifest.py +7 -4

run.do hdl/testbench/pcie/run.do +15 -0

wave.do hdl/testbench/pcie/wave.do +851 -0

No files found.
--- a/hdl/testbench/pcie/Makefile
+++ b/hdl/testbench/pcie/Makefile
--- a/hdl/testbench/pcie/Manifest.py
+++ b/hdl/testbench/pcie/Manifest.py
@@ -18,13 +18,16 @@ def __import_verilog_lib():

 target = "xilinx"
 action = "simulation"
-vlog_opt = "-i ../../sim/pcie -d SIMULATION"
+#pickup correct top file
+syn_device = "xc7k325t"
+
+vlog_opt = "+incdir+../../sim/pcie +define+SIMULATION"
 # ENABLE_GT has to be set until I figure out a way
 # to force ISIM to work in PIPE simulation mode
-vlog_opt += " -d ENABLE_GT"
+#vlog_opt += " +define+ENABLE_GT"
 # DDR model options
-vlog_opt += " -i ../../sim/ddr_model -d x1Gb -d sg125 -d x8"
-vsim_opt = "-testplusarg TESTNAME=tf64_pcie_axi"
+vlog_opt += " +incdir+../../sim/ddr_model +define+x1Gb +define+sg125 +define+x8"
+vsim_opt = "+TESTNAME=tf64_pcie_axi -t fs -novopt +notimingchecks -L unisims_ver -L secureip -L unimacro_ver glbl"

 __import_verilog_lib()
 files = ["board.v",

--- a/hdl/testbench/pcie/run.do
+++ b/hdl/testbench/pcie/run.do
+
+vsim -novopt +TESTNAME=tf64_pcie_axi -t fs +notimingchecks -L work \
+    -L unisims_ver -L secureip -L unimacro_ver work.board glbl
+
+log -r /*
+
+radix hex
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+#add signals to wave window
+do wave.do
+
+run -all
--- a/hdl/testbench/pcie/wave.do
+++ b/hdl/testbench/pcie/wave.do