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AMC FMC Carrier AFC
Commit 713e937a authored by Aylons's avatar Aylons
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Added pinout generator file 

THe python script that generates CSV and the ODS file for general pin
verification and as a design helper were added to the design reports folder.
parent e9e0f8e5
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design_reports/scripts/mgt_options.csv 0 → 100644
View file @ 713e937a
IC2;A13;Tx116_0_N;C195;1;DP1.DP3_C2M_N;J15A;a31;end
IC2;A13;Tx116_0_N;C778;1;GTP0_TX_N;J2;f10;end
IC2;A15;Tx116_2_N;C185;1;DP1.DP1_C2M_N;J15A;a23;end
IC2;A15;Tx116_2_N;C786;1;GTP2_TX_N;J2;f8;end
IC2;A17;Tx116_3_N;C179;1;DP1.DP0_C2M_N;J15A;c3;end
IC2;A17;Tx116_3_N;C790;1;GTP3_TX_N;J2;f7;end
IC2;A19;Tx216_3_N;C343;1;PIPE1.Tx7_N;P1;66;end
IC2;A21;Tx216_2_N;C347;1;PIPE1.Tx6_N;P1;60;end
IC2;A23;Tx216_0_N;C335;1;PIPE1.Tx4_N;P1;45;end
IC2;AG14;MGT113_CLK0_P;C411;1;MGT.FLEX_GTP113_CLK0_P$;IC73;81;end
IC2;AG16;MGT113_CLK1_P;C402;1;MGT.FLEX_GTP113_CLK1_P$;IC51;1;end
IC2;AG18;MGT213_CLK1_P;C219;1;MGT.FLEX_GTP213_CLK1_P$;IC85;1;end
IC2;AG18;MGT213_CLK1_P;C840;1;GBT2.GBTCLK1_M2C_P$;J15B;b20;end
IC2;AG20;MGT213_CLK0_P;C202;1;GBT2.GBTCLK0_M2C_P$;J15B;d4;end
IC2;AG20;MGT213_CLK0_P;C397;1;MGT.125_GTP213_CLK0_P$;IC38;1;end
IC2;AG20;MGT213_CLK0_P;C792;1;GTP4-7_CLK_IN_P;J2;a5;end
IC2;AH14;MGT113_CLK0_N;C413;1;MGT.FLEX_GTP113_CLK0_N$;IC73;82;end
IC2;AH16;MGT113_CLK1_N;C409;1;MGT.FLEX_GTP113_CLK1_N$;IC51;2;end
IC2;AH18;MGT213_CLK1_N;C220;1;MGT.FLEX_GTP213_CLK1_N$;IC85;2;end
IC2;AH18;MGT213_CLK1_N;C841;1;GBT2.GBTCLK1_M2C_N$;J15B;b21;end
IC2;AH20;MGT213_CLK0_N;C203;1;GBT2.GBTCLK0_M2C_N$;J15B;d5;end
IC2;AH20;MGT213_CLK0_N;C399;1;MGT.125_GTP213_CLK0_N$;IC38;2;end
IC2;AH20;MGT213_CLK0_N;C794;1;GTP4-7_CLK_IN_N;J2;b5;end
IC2;AJ13;Rx113_3_P;C223;1;PORT0.Rx0_P;C883;2;RxC0_P;J18;1;end
IC2;AJ13;Rx113_3_P;C223;1;PORT0.Rx0_P;P1;14;end
IC2;AJ13;Rx113_3_P;C332;1;PIPE2.Rx11_P;P1;106;end
IC2;AJ15;Rx113_2_P;C228;1;PORT1.Rx1_P;P1;23;end
IC2;AJ15;Rx113_2_P;C328;1;PIPE2.Rx10_P;P1;100;end
IC2;AJ17;Rx113_0_P;C320;1;PIPE2.Rx8_P;P1;88;end
IC2;AJ17;Rx113_0_P;C590;2;PORT3.Rx3_P;P1;38;end
IC2;AJ19;Rx213_1_P;C206;1;DP2.DP1_M2C_P;J15B;a2;end
IC2;AJ19;Rx213_1_P;C803;1;GTP6_RX_P;J2;c4;end
IC2;AJ19;Rx213_1_P;C828;1;Rx14_P;P1;124;end
IC2;AJ21;Rx213_3_P;C630;1;DP2.DP3_M2C_P;J15B;a10;end
IC2;AJ21;Rx213_3_P;C811;1;GTP4_RX_P;J2;c6;end
IC2;AJ21;Rx213_3_P;C836;1;Rx15_P;P1;130;end
IC2;AK13;Rx113_3_N;C224;1;PORT0.Rx0_N;C884;2;RxC0_N;J19;1;end
IC2;AK13;Rx113_3_N;C224;1;PORT0.Rx0_N;P1;15;end
IC2;AK13;Rx113_3_N;C333;1;PIPE2.Rx11_N;P1;105;end
IC2;AK15;Rx113_2_N;C329;1;PIPE2.Rx10_N;P1;99;end
IC2;AK15;Rx113_2_N;C625;1;PORT1.Rx1_N;P1;24;end
IC2;AK17;Rx113_0_N;C321;1;PIPE2.Rx8_N;P1;87;end
IC2;AK17;Rx113_0_N;C751;2;PORT3.Rx3_N;P1;39;end
IC2;AK19;Rx213_1_N;C207;1;DP2.DP1_M2C_N;J15B;a3;end
IC2;AK19;Rx213_1_N;C804;1;GTP6_RX_N;J2;d4;end
IC2;AK19;Rx213_1_N;C829;1;Rx14_N;P1;123;end
IC2;AK21;Rx213_3_N;C632;1;DP2.DP3_M2C_N;J15B;a11;end
IC2;AK21;Rx213_3_N;C812;1;GTP4_RX_N;J2;d6;end
IC2;AK21;Rx213_3_N;C837;1;Rx15_N;P1;129;end
IC2;AL14;Tx113_2_P;C225;1;PORT1.Tx1_P;P1;20;end
IC2;AL14;Tx113_2_P;C326;1;PIPE2.Tx10_P;P1;103;end
IC2;AL16;Rx113_1_P;C324;1;PIPE2.Rx9_P;P1;94;end
IC2;AL16;Rx113_1_P;C455;2;PORT2.Rx2_P;P1;32;end
IC2;AL18;Rx213_0_P;C200;1;DP2.DP0_M2C_P;J15B;c6;end
IC2;AL18;Rx213_0_P;C798;1;GTP5_RX_P;J2;c5;end
IC2;AL18;Rx213_0_P;C824;1;Rx12_P;P1;112;end
IC2;AL20;Rx213_2_P;C631;1;DP2.DP2_M2C_P;J15B;a6;end
IC2;AL20;Rx213_2_P;C807;1;GTP7_RX_P;J2;c3;end
IC2;AL20;Rx213_2_P;C832;1;Rx13_P;P1;118;end
IC2;AL22;Tx213_2_P;C627;1;DP2.DP2_C2M_P;J15B;a26;end
IC2;AL22;Tx213_2_P;C805;1;GTP7_TX_P;J2;e3;end
IC2;AL22;Tx213_2_P;C830;1;Tx13_P;P1;121;end
IC2;AM14;Tx113_2_N;C227;1;PORT1.Tx1_N;P1;21;end
IC2;AM14;Tx113_2_N;C327;1;PIPE2.Tx10_N;P1;102;end
IC2;AM16;Rx113_1_N;C325;1;PIPE2.Rx9_N;P1;93;end
IC2;AM16;Rx113_1_N;C512;2;PORT2.Rx2_N;P1;33;end
IC2;AM18;Rx213_0_N;C201;1;DP2.DP0_M2C_N;J15B;c7;end
IC2;AM18;Rx213_0_N;C800;1;GTP5_RX_N;J2;d5;end
IC2;AM18;Rx213_0_N;C825;1;Rx12_N;P1;111;end
IC2;AM20;Rx213_2_N;C633;1;DP2.DP2_M2C_N;J15B;a7;end
IC2;AM20;Rx213_2_N;C808;1;GTP7_RX_N;J2;d3;end
IC2;AM20;Rx213_2_N;C833;1;Rx13_N;P1;117;end
IC2;AM22;Tx213_2_N;C629;1;DP2.DP2_C2M_N;J15B;a27;end
IC2;AM22;Tx213_2_N;C806;1;GTP7_TX_N;J2;f3;end
IC2;AM22;Tx213_2_N;C831;1;Tx13_N;P1;120;end
IC2;AN13;Tx113_3_P;C221;1;PORT0.Tx0_P;C886;2;TxC0_P;J21;1;end
IC2;AN13;Tx113_3_P;C221;1;PORT0.Tx0_P;P1;11;end
IC2;AN13;Tx113_3_P;C330;1;PIPE2.Tx11_P;P1;109;end
IC2;AN15;Tx113_1_P;C322;1;PIPE2.Tx9_P;P1;97;end
IC2;AN15;Tx113_1_P;C575;2;PORT2.Tx2_P;P1;29;end
IC2;AN17;Tx113_0_P;C318;1;PIPE2.Tx8_P;P1;91;end
IC2;AN17;Tx113_0_P;C753;2;PORT3.Tx3_P;P1;35;end
IC2;AN19;Tx213_0_P;C198;1;DP2.DP0_C2M_P;J15B;c2;end
IC2;AN19;Tx213_0_P;C795;1;GTP5_TX_P;J2;e5;end
IC2;AN19;Tx213_0_P;C822;1;Tx12_P;P1;115;end
IC2;AN21;Tx213_1_P;C204;1;DP2.DP1_C2M_P;J15B;a22;end
IC2;AN21;Tx213_1_P;C801;1;GTP6_TX_P;J2;e4;end
IC2;AN21;Tx213_1_P;C826;1;Tx14_P;P1;127;end
IC2;AN23;Tx213_3_P;C626;1;DP2.DP3_C2M_P;J15B;a30;end
IC2;AN23;Tx213_3_P;C809;1;GTP4_TX_P;J2;e6;end
IC2;AN23;Tx213_3_P;C834;1;Tx15_P;P1;133;end
IC2;AP13;Tx113_3_N;C222;1;PORT0.Tx0_N;C885;2;TxC0_N;J20;1;end
IC2;AP13;Tx113_3_N;C222;1;PORT0.Tx0_N;P1;12;end
IC2;AP13;Tx113_3_N;C331;1;PIPE2.Tx11_N;P1;108;end
IC2;AP15;Tx113_1_N;C323;1;PIPE2.Tx9_N;P1;96;end
IC2;AP15;Tx113_1_N;C514;2;PORT2.Tx2_N;P1;30;end
IC2;AP17;Tx113_0_N;C319;1;PIPE2.Tx8_N;P1;90;end
IC2;AP17;Tx113_0_N;C752;2;PORT3.Tx3_N;P1;36;end
IC2;AP19;Tx213_0_N;C199;1;DP2.DP0_C2M_N;J15B;c3;end
IC2;AP19;Tx213_0_N;C796;1;GTP5_TX_N;J2;f5;end
IC2;AP19;Tx213_0_N;C823;1;Tx12_N;P1;114;end
IC2;AP21;Tx213_1_N;C205;1;DP2.DP1_C2M_N;J15B;a23;end
IC2;AP21;Tx213_1_N;C802;1;GTP6_TX_N;J2;f4;end
IC2;AP21;Tx213_1_N;C827;1;Tx14_N;P1;126;end
IC2;AP23;Tx213_3_N;C628;1;DP2.DP3_C2M_N;J15B;a31;end
IC2;AP23;Tx213_3_N;C810;1;GTP4_TX_N;J2;f6;end
IC2;AP23;Tx213_3_N;C835;1;Tx15_N;P1;132;end
IC2;B13;Tx116_0_P;C194;1;DP1.DP3_C2M_P;J15A;a30;end
IC2;B13;Tx116_0_P;C777;1;GTP0_TX_P;J2;e10;end
IC2;B15;Tx116_2_P;C184;1;DP1.DP1_C2M_P;J15A;a22;end
IC2;B15;Tx116_2_P;C785;1;GTP2_TX_P;J2;e8;end
IC2;B17;Tx116_3_P;C178;1;DP1.DP0_C2M_P;J15A;c2;end
IC2;B17;Tx116_3_P;C789;1;GTP3_TX_P;J2;e7;end
IC2;B19;Tx216_3_P;C342;1;PIPE1.Tx7_P;P1;65;end
IC2;B21;Tx216_2_P;C346;1;PIPE1.Tx6_P;P1;59;end
IC2;B23;Tx216_0_P;C334;1;PIPE1.Tx4_P;P1;44;end
IC2;C14;Tx116_1_N;C191;1;DP1.DP2_C2M_N;J15A;a27;end
IC2;C14;Tx116_1_N;C782;1;GTP1_TX_N;J2;f9;end
IC2;C16;Rx116_2_N;C187;1;DP1.DP1_M2C_N;J15A;a3;end
IC2;C16;Rx116_2_N;C788;1;GTP2_RX_N;J2;d8;end
IC2;C18;Rx216_3_N;C345;1;PIPE1.Rx7_N;P1;69;end
IC2;C20;Rx216_1_N;C341;1;PIPE1.Rx5_N;P1;54;end
IC2;C22;Tx216_1_N;C339;1;PIPE1.Tx5_N;P1;51;end
IC2;D14;Tx116_1_P;C190;1;DP1.DP2_C2M_P;J15A;a26;end
IC2;D14;Tx116_1_P;C781;1;GTP1_TX_P;J2;e9;end
IC2;D16;Rx116_2_P;C186;1;DP1.DP1_M2C_P;J15A;a2;end
IC2;D16;Rx116_2_P;C787;1;GTP2_RX_P;J2;c8;end
IC2;D18;Rx216_3_P;C344;1;PIPE1.Rx7_P;P1;68;end
IC2;D20;Rx216_1_P;C340;1;PIPE1.Rx5_P;P1;53;end
IC2;D22;Tx216_1_P;C338;1;PIPE1.Tx5_P;P1;50;end
IC2;E13;Rx116_0_N;C197;1;DP1.DP3_M2C_N;J15A;a11;end
IC2;E13;Rx116_0_N;C780;1;GTP0_RX_N;J2;d10;end
IC2;E15;Rx116_1_N;C193;1;DP1.DP2_M2C_N;J15A;a7;end
IC2;E15;Rx116_1_N;C784;1;GTP1_RX_N;J2;d9;end
IC2;E17;Rx116_3_N;C181;1;DP1.DP0_M2C_N;J15A;c7;end
IC2;E17;Rx116_3_N;C793;1;GTP3_RX_N;J2;d7;end
IC2;E19;Rx216_2_N;C349;1;PIPE1.Rx6_N;P1;63;end
IC2;E21;Rx216_0_N;C337;1;PIPE1.Rx4_N;P1;48;end
IC2;F13;Rx116_0_P;C196;1;DP1.DP3_M2C_P;J15A;a10;end
IC2;F13;Rx116_0_P;C779;1;GTP0_RX_P;J2;c10;end
IC2;F15;Rx116_1_P;C192;1;DP1.DP2_M2C_P;J15A;a6;end
IC2;F15;Rx116_1_P;C783;1;GTP1_RX_P;J2;c9;end
IC2;F17;Rx116_3_P;C180;1;DP1.DP0_M2C_P;J15A;c6;end
IC2;F17;Rx116_3_P;C791;1;GTP3_RX_P;J2;c7;end
IC2;F19;Rx216_2_P;C348;1;PIPE1.Rx6_P;P1;62;end
IC2;F21;Rx216_0_P;C336;1;PIPE1.Rx4_P;P1;47;end
IC2;G14;MGT116_CLK1_N;C183;1;GBT1.GBTCLK0_M2C_N$;J15A;d5;end
IC2;G14;MGT116_CLK1_N;C839;1;MGT.FLEX_GTP116_CLK1_N$;IC83;2;end
IC2;G16;MGT116_CLK0_N;C189;1;GBT1.GBTCLK1_M2C_N$;J15A;b21;end
IC2;G16;MGT116_CLK0_N;C799;1;GTP0-3_CLK_IN_N;J2;b9;end
IC2;G18;MGT216_CLK0_N;C396;1;MGT.FCLK_GTP216_CLK0_N$;C815;1;FCLKA_N;P1;81;end
IC2;G20;MGT216_CLK1_N;C463;1;MGT.FLEX_GTP216_CLK1_N$;IC51;4;end
IC2;H14;MGT116_CLK1_P;C182;1;GBT1.GBTCLK0_M2C_P$;J15A;d4;end
IC2;H14;MGT116_CLK1_P;C838;1;MGT.FLEX_GTP116_CLK1_P$;IC83;1;end
IC2;H16;MGT116_CLK0_P;C188;1;GBT1.GBTCLK1_M2C_P$;J15A;b20;end
IC2;H16;MGT116_CLK0_P;C797;1;GTP0-3_CLK_IN_P;J2;a9;end
IC2;H18;MGT216_CLK0_P;C218;1;MGT.FCLK_GTP216_CLK0_P$;C776;1;FCLKA_P;P1;80;end
IC2;H20;MGT216_CLK1_P;C461;1;MGT.FLEX_GTP216_CLK1_P$;IC51;3;end
design_reports/scripts/netlist_read.py 0 → 100644
View file @ 713e937a
#!/usr/bin/env python3
# AFC Pinout helper script
# Copyright (C) 2020 CNPEM
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
# This scripts generates CSV that make it easy to analyse pinout data
# for the FPGA and the LPC ICs in the AFC. It also allows for quick
# checks on the RTM connector pinout, comparing it to net names
# connected to it. It also automatically generates assembly option
# tables for the MGTs, following the different options and setting
# which capacitors enable them.
#
# The script expects a project-wide Cadnetix Netlist file as exported
# by Altium. Please remember compiling the project before generating
# the netlist!
#
# The CSVs are supposed to be used as inputs for the ODS table
# avilable in the project to correlate them with IC pin functions and
# connectors standards
import itertools
import csv
class Netlist:
def __init__(self, file):
self.nodes = {}
with open(file, 'r+', encoding="latin-1") as netlist:
for line in netlist:
if "NODENAME" in line:
break
for line in netlist:
if "EOS" in line:
break
if "NODENAME" in line:
nodename = line.split()[1]
self.nodes[nodename]=[]
line2 = next(netlist)
connection = line2.split()
for ic, pin in zip(connection[0::2], connection[1::2]):
self.nodes[nodename].append((ic,pin))
def write_part_nets(self, file, part):
with open(file,'w',newline='') as csvfile:
csvwriter = csv.writer(csvfile, delimiter =';')
for node, connections in self.nodes.items():
for connection in connections:
if connection[0] in part:
csvwriter.writerow((connection[0],connection[1],node))
def get_node_from_port(self, port):
for node, ports in self.nodes.items():
if port in ports:
return node
#given a two-pin part and its pin, returns the node in the other pin in a netlist
def cross_twopin(self, port):
(part, pin) = port
if pin == '1':
new_port = (part,'2')
else:
new_port = (part,'1')
new_node = self.get_node_from_port(new_port)
return(new_port,new_node)
#Follow all resistors and capacitors to follow a signal from IC to IC or Connector
def follow_asm_opt(self, start_port, start_node=None, path=[]):
if start_node == None:
start_node = self.get_node_from_port(start_port)
if start_node == None:
return [start_port,"end"]
path = path + [(start_port,start_node)]
paths = []
#scan all pins in this node
for port in self.nodes[start_node]:
#prevent coming back
if (port == start_port):
continue
(part,pin) = port
# As the end of the graph is not known beforehand, we walk until we find something which is not 2-pi
if is_twopin(part):
(next_port,node) = self.cross_twopin(port)
#depth first search. Not the most efficient, but more than enough for any reasonable and most unreasonable circuits
new_paths = self.follow_asm_opt(next_port,node,path)
for new_path in new_paths:
paths.append(new_path)
else:
path = path + [(port,"end")]
paths.append(path)
return paths
#check if a part is two-pin passive (L, C or R) by name standard
def is_twopin(part):
if(part[0] in ('R','L','C')):
return part[1:].isnumeric()
else:
return False;
# This function follows all the possible paths for a given signal and writes it to a CSV. Do not use it in power rails or pulled-up signals, as it will follow all nodes on that rail
def write_mgt_options(netlist):
output_file = "mgt_options.csv"
with open('afc_mgt_pins.csv') as in_file:
csv_reader = csv.reader(in_file, delimiter=',')
mgt_ports = []
for row in csv_reader:
mgt_ports.append(('IC2',row[0]))
mounting_options=[]
for port in mgt_ports:
mounting_options.append(netlist.follow_asm_opt(port))
try:
with open(output_file,"w") as out_file:
csv_writer = csv.writer(out_file,delimiter=';')
for mgt_port in mounting_options:
for option in mgt_port:
line = []
for ((part,pin),node)in option:
line=line+[part]+[pin]+[node]
csv_writer.writerow(line)
except ValueError:
print("ValueError, option: " + str(option))
def write_rtm_resistors(netlist):
output_file = "rtm_resistor.csv"
parts = ("R215","R249","R251","R253","R385","R386","R388","R390")
netlist.write_part_nets(output_file, parts)
def write_rtm_connectors(netlist):
output_file = "rtm_connector.csv"
parts = ("J1","J2")
netlist.write_part_nets(output_file, parts)
def write_lpc_connections(netlist):
output_file = "lpc_connection.csv"
parts = "IC1"
netlist.write_part_nets(output_file,parts)
def write_fpga_connections(netlist):
output_file = "fpga_connection.csv"
parts = "IC2"
netlist.write_part_nets(output_file,parts)
input_file = "AMC_FMC_Carrier.NET"
afc = Netlist(input_file)
write_fpga_connections(afc)
write_rtm_connectors(afc)
write_lpc_connections(afc)
write_rtm_resistors(afc)
write_mgt_options(afc)
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