Schematic RC 6
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Developer
Changed file name: FPGA_HPC2 -> FPGA_HPC2_RTM
Pin swapping of diff MLVDS lanes
Fixed signals names of MMC JTAG/debug connector (it was's connected to MMC)
New MLVDS single-ended signals names at FPGA_SDRAM.SchDoc (MLVDS I or O)
Fixed harness type of JTAG at FMC_connector.SchDoc.
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