Work on gn4124 module.

Adding exception class, comments, etc...

common/gn4124.py

@@ -18,6 +18,12 @@ import csr
 # Class to access the GN4124 (PCIe bridge) chip.
 # It uses the CSR class.
 
+class GN4124OperationError(Exception):
+    def __init__(self, msg):
+        self.msg = msg
+    def __str__(self):
+        return ("GN4124 produced the error: %s" %(msg))
+
 class CGN4124:
 
     # Host registers (BAR C), for DMA items storage on the host side
@@ -79,43 +85,42 @@ class CGN4124:
         self.pages = [addr << 12 for addr in self.pages]
         # Configure GN4124 to generate interrupt (MSI) on rising edge of GPIO 8
         self.set_interrupt_config()
-        # Enable interrupt from gn4124
+        # Enable interrupt from gn4124 in the driver
         self.bus.irqena()
 
-    # Set local bus frequency
+    # Set GN4124 local bus frequency
     def set_local_bus_freq(self, freq):
         # freq in MHz
         # LCLK = (25MHz*(DIVFB+1))/(DIVOT+1)
         # DIVFB = 31
         # DIVOT = (800/LCLK)-1
         divot = int(round((800/freq)-1,0))
-        #print '%d' % divot
+        #print '[GN4124] DIVOT=%d' % divot
         data = 0xe001f00c + (divot << 4)
-        #print '%.8X' % data
-        #print 'Set local bus freq to %dMHz' % int(round(800/(divot+1),0))
+        #print '[GN4124] CLK_CSR reg=0x%.8X' % data
+        #print '[GN4124] Set local bus freq to %dMHz' % int(round(800/(divot+1),0))
         self.wr_reg(self.GN4124_BAR, self.R_CLK_CSR, data)
 
-    # Get local bus frequency
+    # Get GN4142 local bus frequency
     #   return: frequency in MHz
     def get_local_bus_freq(self):
         reg = self.rd_reg(self.GN4124_BAR, self.R_CLK_CSR)
         divot = ((reg & self.CLK_CSR_DIVOT_MASK)>>4)
         return (800/(divot + 1))
 
-    # Get physical addresses of the pages allocated to GN4124
+    # Get physical addresses of the host memory pages allocated to GN4124
     def get_physical_addr(self):
         return self.pages
 
     # Wait for interrupt
     def wait_irq(self):
-        # Add here reading of the interrupt source (once the irq core will be present)
         return self.bus.irqwait()
 
     # GN4124 RSTOUT33 assert/de-assert cycle
     def rstout33_cycle(self):
-        # assert RSTOUT33 pin
+        # Assert RSTOUT33 pin
         self.wr_reg(self.GN4124_BAR, self.R_PCI_SYS_CFG, 0x00021040)
-        # de-assert RSTOUT33 pin
+        # De-assert RSTOUT33 pin
         self.wr_reg(self.GN4124_BAR, self.R_PCI_SYS_CFG, 0x00025000)
 
     # GN4124 interrupt configuration
@@ -135,8 +140,8 @@ class CGN4124:
     def get_dma_status(self):
         reg = self.dma_csr.rd_reg(self.R_DMA_STA)
         if(reg > len(self.DMA_STA)):
-            print("DMA status register : %.8X") % reg
-            raise Exception('Invalid DMA status')
+            #print("[GN4142] DMA status register : 0x%.8X") % reg
+            raise GN4124OperationError("Invalid DMA status")
         else:
             return self.DMA_STA[reg]
 
@@ -147,7 +152,7 @@ class CGN4124:
     #   3 = D4 C3 B2 A1 (invert bytes)
     def set_dma_swap(self, swap):
         if(swap > 3):
-            raise Exception('Invalid swapping configuration : %d') % swap
+            raise GN4124OperationError('Invalid swapping configuration : %d') % swap
         else:
             self.dma_csr.wr_reg(self.R_CTL, (swap << self.DMA_CTL_SWAP))