Work on gn4124 module.

common/gn4124.py

-#!/usr/bin/python
+#!   /usr/bin/env   python
+#    coding: utf8
 
+# Copyright CERN, 2011
+# Author: Matthieu Cattin (CERN)
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+# Last modifications: 27/4/2012
+
+# Import standard modules
 import sys
-import rr
 import time
+
+# Import specific modules
+import rr
 import csr
 
+# Class to access the GN4124 (PCIe bridge) chip.
+# It uses the CSR class.
+
 class CGN4124:
 
-    # Host registers (BAR12), for DMA items storage
+    # Host registers (BAR C), for DMA items storage on the host side
     HOST_BAR = 0xC
     HOST_DMA_CARRIER_START_ADDR = 0x00
     HOST_DMA_HOST_START_ADDR_L = 0x04
@@ -17,7 +30,7 @@ class CGN4124:
     HOST_DMA_NEXT_ITEM_ADDR_H = 0x14
     HOST_DMA_ATTRIB = 0x18
 
-    # GN4124 chip registers (BAR4)
+    # GN4124 chip registers (BAR 4)
     GN4124_BAR = 0x4
     R_PCI_SYS_CFG = 0x800
     R_CLK_CSR = 0x808
@@ -32,7 +45,7 @@ class CGN4124:
     INT_CFG0_GPIO = 15
     GPIO_INT_SRC = 8
 
-    # GN4124 core registers (BAR0)
+    # GN4124 core registers (BAR 0)
     R_DMA_CTL = 0x00
     R_DMA_STA = 0x04
     R_DMA_CARRIER_START_ADDR = 0x08
@@ -56,14 +69,15 @@ class CGN4124:
     def wr_reg(self, bar, addr, value):
         self.bus.iwrite(bar, addr, 4, value)
 
-    def __init__(self, bus, csr_addr):
+    def __init__(self, bus, csr):
         self.bus = bus
-        self.dma_csr = csr.CCSR(bus, csr_addr)
+        self.dma_csr = csr
         self.dma_item_cnt = 0
-        # Get page list
+        # Get pointer list to host memory pages (allocated by the driver)
         self.pages = self.bus.getplist()
         # Shift by 12 to get the 32-bit physical addresses
         self.pages = [addr << 12 for addr in self.pages]
+        # Configure GN4124 to generate interrupt (MSI) on rising edge of GPIO 8
         self.set_interrupt_config()
         # Enable interrupt from gn4124
         self.bus.irqena()