Two important changes to wishbone file: 1-the TBMR read request output…
Two important changes to wishbone file: 1-the TBMR read request output reg_tb_rd_req_p_o is presend in the conv_regs.vhd in the master branch, but no indication of how it has been added in the corresponding *.wb file. The conclusion was that the *.vhd file was either generated from a different *.wb file or has been modified manually. The right expression, ack_read=port_out, is now used in the *.wb file and fixes the problem. 2-Memory map has been modified to add PCB version information. Additionally a new type of error has been defined: flim_err and fwdg_err. To do so, a new error register has been created to put all error types together. The SR register now provides the hw version in addition to previous information, apart from errors.
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