Commit ba9673e5 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Two important changes to wishbone file: 1-the TBMR read request output…

Two important changes to wishbone file: 1-the TBMR read request output reg_tb_rd_req_p_o is presend in the conv_regs.vhd in the master branch, but no indication of how it has been added in the corresponding *.wb file. The conclusion was that the *.vhd file was either generated from a different *.wb file or has been modified manually. The right expression, ack_read=port_out, is now used in the *.wb file and fixes the problem. 2-Memory map has been modified to add PCB version information. Additionally a new type of error has been defined: flim_err and fwdg_err. To do so, a new error register has been created to put all error types together. The SR register now provides the hw version in addition to previous information, apart from errors.
parent eb610e84
......@@ -2,17 +2,17 @@
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 12/20/16 14:58:28
* Author : auto-generated by wbgen2 from .\conv_regs.wb
* Created : 02/01/17 15:43:01
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS__\CONV_REGS_WB
#define __WBGEN2_REGDEFS__\CONV_REGS_WB
#include <inttypes.h>
......@@ -53,20 +53,34 @@
#define REG_SR_RTM_W(value) WBGEN2_GEN_WRITE(value, 16, 6)
#define REG_SR_RTM_R(reg) WBGEN2_GEN_READ(reg, 16, 6)
/* definitions for field: I2C communication watchdog timeout error in reg: SR */
#define REG_SR_I2C_WDTO WBGEN2_GEN_MASK(22, 1)
/* definitions for field: Hardware version in reg: SR */
#define REG_SR_HWVERS_MASK WBGEN2_GEN_MASK(22, 4)
#define REG_SR_HWVERS_SHIFT 22
#define REG_SR_HWVERS_W(value) WBGEN2_GEN_WRITE(value, 22, 4)
#define REG_SR_HWVERS_R(reg) WBGEN2_GEN_READ(reg, 22, 4)
/* definitions for field: White Rabbit present in reg: SR */
#define REG_SR_WRPRES WBGEN2_GEN_MASK(23, 1)
#define REG_SR_WRPRES WBGEN2_GEN_MASK(26, 1)
/* definitions for field: I2C communication error in reg: SR */
#define REG_SR_I2C_ERR WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ERR */
/* definitions for field: Pulse missed error in reg: SR */
#define REG_SR_PMISSE_MASK WBGEN2_GEN_MASK(25, 6)
#define REG_SR_PMISSE_SHIFT 25
#define REG_SR_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 25, 6)
#define REG_SR_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 25, 6)
/* definitions for field: I2C communication watchdog timeout error in reg: ERR */
#define REG_ERR_I2C_WDTO WBGEN2_GEN_MASK(0, 1)
/* definitions for field: I2C communication error in reg: ERR */
#define REG_ERR_I2C_ERR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Frequency error in reg: ERR */
#define REG_ERR_FLIM_PMISSE_MASK WBGEN2_GEN_MASK(2, 6)
#define REG_ERR_FLIM_PMISSE_SHIFT 2
#define REG_ERR_FLIM_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define REG_ERR_FLIM_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Frequency watchdog error in reg: ERR */
#define REG_ERR_FWDG_PMISSE_MASK WBGEN2_GEN_MASK(8, 6)
#define REG_ERR_FWDG_PMISSE_SHIFT 8
#define REG_ERR_FWDG_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define REG_ERR_FWDG_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for register: CR */
......@@ -289,90 +303,92 @@
#define REG_REG_BIDR 0x00000000
/* [0x4]: REG SR */
#define REG_REG_SR 0x00000004
/* [0x8]: REG CR */
#define REG_REG_CR 0x00000008
/* [0xc]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x0000000c
/* [0x10]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000010
/* [0x14]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000014
/* [0x18]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x00000018
/* [0x1c]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x0000001c
/* [0x20]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000020
/* [0x24]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000024
/* [0x28]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x00000028
/* [0x2c]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x0000002c
/* [0x30]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000030
/* [0x34]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000034
/* [0x38]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x00000038
/* [0x3c]: REG TVLR */
#define REG_REG_TVLR 0x0000003c
/* [0x40]: REG TVHR */
#define REG_REG_TVHR 0x00000040
/* [0x44]: REG TBMR */
#define REG_REG_TBMR 0x00000044
/* [0x48]: REG TBCYR */
#define REG_REG_TBCYR 0x00000048
/* [0x4c]: REG TBTLR */
#define REG_REG_TBTLR 0x0000004c
/* [0x50]: REG TBTHR */
#define REG_REG_TBTHR 0x00000050
/* [0x54]: REG TBCSR */
#define REG_REG_TBCSR 0x00000054
/* [0x58]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x00000058
/* [0x5c]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x0000005c
/* [0x60]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000060
/* [0x64]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000064
/* [0x68]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x00000068
/* [0x6c]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x0000006c
/* [0x70]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000070
/* [0x74]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000074
/* [0x78]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x00000078
/* [0x7c]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x0000007c
/* [0x80]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000080
/* [0x84]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000084
/* [0x88]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x00000088
/* [0x8c]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x0000008c
/* [0x90]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000090
/* [0x94]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000094
/* [0x98]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x00000098
/* [0x9c]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x0000009c
/* [0xa0]: REG LSR */
#define REG_REG_LSR 0x000000a0
/* [0xa4]: REG OSWR */
#define REG_REG_OSWR 0x000000a4
/* [0xa8]: REG UIDLR */
#define REG_REG_UIDLR 0x000000a8
/* [0xac]: REG UIDHR */
#define REG_REG_UIDHR 0x000000ac
/* [0xb0]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b0
/* [0x8]: REG ERR */
#define REG_REG_ERR 0x00000008
/* [0xc]: REG CR */
#define REG_REG_CR 0x0000000c
/* [0x10]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x00000010
/* [0x14]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000014
/* [0x18]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000018
/* [0x1c]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x0000001c
/* [0x20]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x00000020
/* [0x24]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000024
/* [0x28]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000028
/* [0x2c]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x0000002c
/* [0x30]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x00000030
/* [0x34]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000034
/* [0x38]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000038
/* [0x3c]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x0000003c
/* [0x40]: REG TVLR */
#define REG_REG_TVLR 0x00000040
/* [0x44]: REG TVHR */
#define REG_REG_TVHR 0x00000044
/* [0x48]: REG TBMR */
#define REG_REG_TBMR 0x00000048
/* [0x4c]: REG TBCYR */
#define REG_REG_TBCYR 0x0000004c
/* [0x50]: REG TBTLR */
#define REG_REG_TBTLR 0x00000050
/* [0x54]: REG TBTHR */
#define REG_REG_TBTHR 0x00000054
/* [0x58]: REG TBCSR */
#define REG_REG_TBCSR 0x00000058
/* [0x5c]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x0000005c
/* [0x60]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x00000060
/* [0x64]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000064
/* [0x68]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000068
/* [0x6c]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x0000006c
/* [0x70]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x00000070
/* [0x74]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000074
/* [0x78]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000078
/* [0x7c]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x0000007c
/* [0x80]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x00000080
/* [0x84]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000084
/* [0x88]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000088
/* [0x8c]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x0000008c
/* [0x90]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x00000090
/* [0x94]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000094
/* [0x98]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000098
/* [0x9c]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x0000009c
/* [0xa0]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x000000a0
/* [0xa4]: REG LSR */
#define REG_REG_LSR 0x000000a4
/* [0xa8]: REG OSWR */
#define REG_REG_OSWR 0x000000a8
/* [0xac]: REG UIDLR */
#define REG_REG_UIDLR 0x000000ac
/* [0xb0]: REG UIDHR */
#define REG_REG_UIDHR 0x000000b0
/* [0xb4]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b4
#endif
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......@@ -100,6 +100,37 @@ peripheral {
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Hardware version";
description = "PCB version - Hardwired on the board \
Only meaningful for HW v4 and over \
Earlier versions show 0 \
e.g. \
0x04 -- hw v4 \
0x05 -- hw v5 \
0x00 -- hw v3 and earlier";
prefix = "hwvers";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Error register
reg {
name = "ERR";
description = "Error Register";
prefix = "err";
field {
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
......@@ -112,15 +143,6 @@ peripheral {
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
......@@ -133,14 +155,29 @@ peripheral {
load = LOAD_EXT;
};
field {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \
name = "Frequency error";
description = "1 -- Input above maximum supported frequency \
0 -- idle \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "flim_pmisse";
type = SLV;
size = 6;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Frequency watchdog error";
description = "1 -- Pulse over maximum pulse count for given frequency' \
0 -- idle \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "pmisse";
prefix = "fwdg_pmisse";
type = SLV;
size = 6;
access_dev = READ_WRITE;
......@@ -149,7 +186,6 @@ peripheral {
};
};
-- Control Register
reg {
name = "CR";
......@@ -407,6 +443,7 @@ peripheral {
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
ack_read = "reg_tb_rd_req_p_o";
};
field {
name = "White Rabbit present";
......
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