Commit ba9673e5 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Two important changes to wishbone file: 1-the TBMR read request output…

Two important changes to wishbone file: 1-the TBMR read request output reg_tb_rd_req_p_o is presend in the conv_regs.vhd in the master branch, but no indication of how it has been added in the corresponding *.wb file. The conclusion was that the *.vhd file was either generated from a different *.wb file or has been modified manually. The right expression, ack_read=port_out, is now used in the *.wb file and fixes the problem. 2-Memory map has been modified to add PCB version information. Additionally a new type of error has been defined: flim_err and fwdg_err. To do so, a new error register has been created to put all error types together. The SR register now provides the hw version in addition to previous information, apart from errors.
parent eb610e84
......@@ -2,17 +2,17 @@
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 12/20/16 14:58:28
* Author : auto-generated by wbgen2 from .\conv_regs.wb
* Created : 02/01/17 15:43:01
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS__\CONV_REGS_WB
#define __WBGEN2_REGDEFS__\CONV_REGS_WB
#include <inttypes.h>
......@@ -53,20 +53,34 @@
#define REG_SR_RTM_W(value) WBGEN2_GEN_WRITE(value, 16, 6)
#define REG_SR_RTM_R(reg) WBGEN2_GEN_READ(reg, 16, 6)
/* definitions for field: I2C communication watchdog timeout error in reg: SR */
#define REG_SR_I2C_WDTO WBGEN2_GEN_MASK(22, 1)
/* definitions for field: Hardware version in reg: SR */
#define REG_SR_HWVERS_MASK WBGEN2_GEN_MASK(22, 4)
#define REG_SR_HWVERS_SHIFT 22
#define REG_SR_HWVERS_W(value) WBGEN2_GEN_WRITE(value, 22, 4)
#define REG_SR_HWVERS_R(reg) WBGEN2_GEN_READ(reg, 22, 4)
/* definitions for field: White Rabbit present in reg: SR */
#define REG_SR_WRPRES WBGEN2_GEN_MASK(23, 1)
#define REG_SR_WRPRES WBGEN2_GEN_MASK(26, 1)
/* definitions for field: I2C communication error in reg: SR */
#define REG_SR_I2C_ERR WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ERR */
/* definitions for field: Pulse missed error in reg: SR */
#define REG_SR_PMISSE_MASK WBGEN2_GEN_MASK(25, 6)
#define REG_SR_PMISSE_SHIFT 25
#define REG_SR_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 25, 6)
#define REG_SR_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 25, 6)
/* definitions for field: I2C communication watchdog timeout error in reg: ERR */
#define REG_ERR_I2C_WDTO WBGEN2_GEN_MASK(0, 1)
/* definitions for field: I2C communication error in reg: ERR */
#define REG_ERR_I2C_ERR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Frequency error in reg: ERR */
#define REG_ERR_FLIM_PMISSE_MASK WBGEN2_GEN_MASK(2, 6)
#define REG_ERR_FLIM_PMISSE_SHIFT 2
#define REG_ERR_FLIM_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define REG_ERR_FLIM_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Frequency watchdog error in reg: ERR */
#define REG_ERR_FWDG_PMISSE_MASK WBGEN2_GEN_MASK(8, 6)
#define REG_ERR_FWDG_PMISSE_SHIFT 8
#define REG_ERR_FWDG_PMISSE_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define REG_ERR_FWDG_PMISSE_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for register: CR */
......@@ -289,90 +303,92 @@
#define REG_REG_BIDR 0x00000000
/* [0x4]: REG SR */
#define REG_REG_SR 0x00000004
/* [0x8]: REG CR */
#define REG_REG_CR 0x00000008
/* [0xc]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x0000000c
/* [0x10]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000010
/* [0x14]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000014
/* [0x18]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x00000018
/* [0x1c]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x0000001c
/* [0x20]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000020
/* [0x24]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000024
/* [0x28]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x00000028
/* [0x2c]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x0000002c
/* [0x30]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000030
/* [0x34]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000034
/* [0x38]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x00000038
/* [0x3c]: REG TVLR */
#define REG_REG_TVLR 0x0000003c
/* [0x40]: REG TVHR */
#define REG_REG_TVHR 0x00000040
/* [0x44]: REG TBMR */
#define REG_REG_TBMR 0x00000044
/* [0x48]: REG TBCYR */
#define REG_REG_TBCYR 0x00000048
/* [0x4c]: REG TBTLR */
#define REG_REG_TBTLR 0x0000004c
/* [0x50]: REG TBTHR */
#define REG_REG_TBTHR 0x00000050
/* [0x54]: REG TBCSR */
#define REG_REG_TBCSR 0x00000054
/* [0x58]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x00000058
/* [0x5c]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x0000005c
/* [0x60]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000060
/* [0x64]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000064
/* [0x68]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x00000068
/* [0x6c]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x0000006c
/* [0x70]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000070
/* [0x74]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000074
/* [0x78]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x00000078
/* [0x7c]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x0000007c
/* [0x80]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000080
/* [0x84]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000084
/* [0x88]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x00000088
/* [0x8c]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x0000008c
/* [0x90]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000090
/* [0x94]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000094
/* [0x98]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x00000098
/* [0x9c]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x0000009c
/* [0xa0]: REG LSR */
#define REG_REG_LSR 0x000000a0
/* [0xa4]: REG OSWR */
#define REG_REG_OSWR 0x000000a4
/* [0xa8]: REG UIDLR */
#define REG_REG_UIDLR 0x000000a8
/* [0xac]: REG UIDHR */
#define REG_REG_UIDHR 0x000000ac
/* [0xb0]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b0
/* [0x8]: REG ERR */
#define REG_REG_ERR 0x00000008
/* [0xc]: REG CR */
#define REG_REG_CR 0x0000000c
/* [0x10]: REG CH1TTLPCR */
#define REG_REG_CH1TTLPCR 0x00000010
/* [0x14]: REG CH2TTLPCR */
#define REG_REG_CH2TTLPCR 0x00000014
/* [0x18]: REG CH3TTLPCR */
#define REG_REG_CH3TTLPCR 0x00000018
/* [0x1c]: REG CH4TTLPCR */
#define REG_REG_CH4TTLPCR 0x0000001c
/* [0x20]: REG CH5TTLPCR */
#define REG_REG_CH5TTLPCR 0x00000020
/* [0x24]: REG CH6TTLPCR */
#define REG_REG_CH6TTLPCR 0x00000024
/* [0x28]: REG CH1BLOPCR */
#define REG_REG_CH1BLOPCR 0x00000028
/* [0x2c]: REG CH2BLOPCR */
#define REG_REG_CH2BLOPCR 0x0000002c
/* [0x30]: REG CH3BLOPCR */
#define REG_REG_CH3BLOPCR 0x00000030
/* [0x34]: REG CH4BLOPCR */
#define REG_REG_CH4BLOPCR 0x00000034
/* [0x38]: REG CH5BLOPCR */
#define REG_REG_CH5BLOPCR 0x00000038
/* [0x3c]: REG CH6BLOPCR */
#define REG_REG_CH6BLOPCR 0x0000003c
/* [0x40]: REG TVLR */
#define REG_REG_TVLR 0x00000040
/* [0x44]: REG TVHR */
#define REG_REG_TVHR 0x00000044
/* [0x48]: REG TBMR */
#define REG_REG_TBMR 0x00000048
/* [0x4c]: REG TBCYR */
#define REG_REG_TBCYR 0x0000004c
/* [0x50]: REG TBTLR */
#define REG_REG_TBTLR 0x00000050
/* [0x54]: REG TBTHR */
#define REG_REG_TBTHR 0x00000054
/* [0x58]: REG TBCSR */
#define REG_REG_TBCSR 0x00000058
/* [0x5c]: REG CH1LTSCYR */
#define REG_REG_CH1LTSCYR 0x0000005c
/* [0x60]: REG CH1LTSTLR */
#define REG_REG_CH1LTSTLR 0x00000060
/* [0x64]: REG CH1LTSTHR */
#define REG_REG_CH1LTSTHR 0x00000064
/* [0x68]: REG CH2LTSCYR */
#define REG_REG_CH2LTSCYR 0x00000068
/* [0x6c]: REG CH2LTSTLR */
#define REG_REG_CH2LTSTLR 0x0000006c
/* [0x70]: REG CH2LTSTHR */
#define REG_REG_CH2LTSTHR 0x00000070
/* [0x74]: REG CH3LTSCYR */
#define REG_REG_CH3LTSCYR 0x00000074
/* [0x78]: REG CH3LTSTLR */
#define REG_REG_CH3LTSTLR 0x00000078
/* [0x7c]: REG CH3LTSTHR */
#define REG_REG_CH3LTSTHR 0x0000007c
/* [0x80]: REG CH4LTSCYR */
#define REG_REG_CH4LTSCYR 0x00000080
/* [0x84]: REG CH4LTSTLR */
#define REG_REG_CH4LTSTLR 0x00000084
/* [0x88]: REG CH4LTSTHR */
#define REG_REG_CH4LTSTHR 0x00000088
/* [0x8c]: REG CH5LTSCYR */
#define REG_REG_CH5LTSCYR 0x0000008c
/* [0x90]: REG CH5LTSTLR */
#define REG_REG_CH5LTSTLR 0x00000090
/* [0x94]: REG CH5LTSTHR */
#define REG_REG_CH5LTSTHR 0x00000094
/* [0x98]: REG CH6LTSCYR */
#define REG_REG_CH6LTSCYR 0x00000098
/* [0x9c]: REG CH6LTSTLR */
#define REG_REG_CH6LTSTLR 0x0000009c
/* [0xa0]: REG CH6LTSTHR */
#define REG_REG_CH6LTSTHR 0x000000a0
/* [0xa4]: REG LSR */
#define REG_REG_LSR 0x000000a4
/* [0xa8]: REG OSWR */
#define REG_REG_OSWR 0x000000a8
/* [0xac]: REG UIDLR */
#define REG_REG_UIDLR 0x000000ac
/* [0xb0]: REG UIDHR */
#define REG_REG_UIDHR 0x000000b0
/* [0xb4]: REG TEMPR */
#define REG_REG_TEMPR 0x000000b4
#endif
......@@ -36,49 +36,50 @@
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">BIDR</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">SR</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">CR</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">CH1TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">CH2TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">CH3TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">CH4TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">CH5TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">CH6TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">CH1BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">CH2BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">CH3BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">CH4BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">CH5BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">CH6BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">TVLR</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">TVHR</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">TBMR</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">TBCYR</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">TBTLR</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">TBTHR</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">TBCSR</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">CH1LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">CH1LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">CH1LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">CH2LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">CH2LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">CH2LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">CH3LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">CH3LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">CH3LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">CH4LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">CH4LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">CH4LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">CH5LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">CH5LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">CH5LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">CH6LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">CH6LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">CH6LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">LSR</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">OSWR</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">UIDLR</a></span><br/>
<span style="margin-left: 20px; ">3.44. <A href="#sect_3_44">UIDHR</a></span><br/>
<span style="margin-left: 20px; ">3.45. <A href="#sect_3_45">TEMPR</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">ERR</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">CR</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">CH1TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">CH2TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">CH3TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">CH4TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">CH5TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">CH6TTLPCR</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">CH1BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">CH2BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">CH3BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">CH4BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">CH5BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">CH6BLOPCR</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">TVLR</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">TVHR</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">TBMR</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">TBCYR</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">TBTLR</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">TBTHR</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">TBCSR</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">CH1LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">CH1LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">CH1LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">CH2LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">CH2LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">CH2LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">CH3LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">CH3LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">CH3LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">CH4LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">CH4LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">CH4LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">CH5LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">CH5LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">CH5LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">CH6LTSCYR</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">CH6LTSTLR</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">CH6LTSTHR</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">LSR</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">OSWR</a></span><br/>
<span style="margin-left: 20px; ">3.44. <A href="#sect_3_44">UIDLR</a></span><br/>
<span style="margin-left: 20px; ">3.45. <A href="#sect_3_45">UIDHR</a></span><br/>
<span style="margin-left: 20px; ">3.46. <A href="#sect_3_46">TEMPR</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -140,6 +141,23 @@ SR
REG
</td>
<td >
<A href="#ERR">ERR</a>
</td>
<td class="td_code">
reg_err
</td>
<td class="td_code">
ERR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#CR">CR</a>
</td>
<td class="td_code">
......@@ -149,9 +167,9 @@ reg_cr
CR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x3
0x4
</td>
<td >
REG
......@@ -166,9 +184,9 @@ reg_ch1ttlpcr
CH1TTLPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x4
0x5
</td>
<td >
REG
......@@ -183,9 +201,9 @@ reg_ch2ttlpcr
CH2TTLPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x5
0x6
</td>
<td >
REG
......@@ -200,9 +218,9 @@ reg_ch3ttlpcr
CH3TTLPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x6
0x7
</td>
<td >
REG
......@@ -217,9 +235,9 @@ reg_ch4ttlpcr
CH4TTLPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x7
0x8
</td>
<td >
REG
......@@ -234,9 +252,9 @@ reg_ch5ttlpcr
CH5TTLPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x8
0x9
</td>
<td >
REG
......@@ -251,9 +269,9 @@ reg_ch6ttlpcr
CH6TTLPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x9
0xa
</td>
<td >
REG
......@@ -268,9 +286,9 @@ reg_ch1blopcr
CH1BLOPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xa
0xb
</td>
<td >
REG
......@@ -285,9 +303,9 @@ reg_ch2blopcr
CH2BLOPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0xb
0xc
</td>
<td >
REG
......@@ -302,9 +320,9 @@ reg_ch3blopcr
CH3BLOPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xc
0xd
</td>
<td >
REG
......@@ -319,9 +337,9 @@ reg_ch4blopcr
CH4BLOPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0xd
0xe
</td>
<td >
REG
......@@ -336,9 +354,9 @@ reg_ch5blopcr
CH5BLOPCR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xe
0xf
</td>
<td >
REG
......@@ -353,9 +371,9 @@ reg_ch6blopcr
CH6BLOPCR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0xf
0x10
</td>
<td >
REG
......@@ -370,9 +388,9 @@ reg_tvlr
TVLR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x10
0x11
</td>
<td >
REG
......@@ -387,9 +405,9 @@ reg_tvhr
TVHR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x11
0x12
</td>
<td >
REG
......@@ -404,9 +422,9 @@ reg_tbmr
TBMR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x12
0x13
</td>
<td >
REG
......@@ -421,9 +439,9 @@ reg_tbcyr
TBCYR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x13
0x14
</td>
<td >
REG
......@@ -438,9 +456,9 @@ reg_tbtlr
TBTLR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x14
0x15
</td>
<td >
REG
......@@ -455,9 +473,9 @@ reg_tbthr
TBTHR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x15
0x16
</td>
<td >
REG
......@@ -472,9 +490,9 @@ reg_tbcsr
TBCSR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x16
0x17
</td>
<td >
REG
......@@ -489,9 +507,9 @@ reg_ch1ltscyr
CH1LTSCYR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x17
0x18
</td>
<td >
REG
......@@ -506,9 +524,9 @@ reg_ch1ltstlr
CH1LTSTLR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x18
0x19
</td>
<td >
REG
......@@ -523,9 +541,9 @@ reg_ch1ltsthr
CH1LTSTHR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x19
0x1a
</td>
<td >
REG
......@@ -540,9 +558,9 @@ reg_ch2ltscyr
CH2LTSCYR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1a
0x1b
</td>
<td >
REG
......@@ -557,9 +575,9 @@ reg_ch2ltstlr
CH2LTSTLR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1b
0x1c
</td>
<td >
REG
......@@ -574,9 +592,9 @@ reg_ch2ltsthr
CH2LTSTHR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1c
0x1d
</td>
<td >
REG
......@@ -591,9 +609,9 @@ reg_ch3ltscyr
CH3LTSCYR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1d
0x1e
</td>
<td >
REG
......@@ -608,9 +626,9 @@ reg_ch3ltstlr
CH3LTSTLR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1e
0x1f
</td>
<td >
REG
......@@ -625,9 +643,9 @@ reg_ch3ltsthr
CH3LTSTHR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x1f
0x20
</td>
<td >
REG
......@@ -642,9 +660,9 @@ reg_ch4ltscyr
CH4LTSCYR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x20
0x21
</td>
<td >
REG
......@@ -659,9 +677,9 @@ reg_ch4ltstlr
CH4LTSTLR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x21
0x22
</td>
<td >
REG
......@@ -676,9 +694,9 @@ reg_ch4ltsthr
CH4LTSTHR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x22
0x23
</td>
<td >
REG
......@@ -693,9 +711,9 @@ reg_ch5ltscyr
CH5LTSCYR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x23
0x24
</td>
<td >
REG
......@@ -710,9 +728,9 @@ reg_ch5ltstlr
CH5LTSTLR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x24
0x25
</td>
<td >
REG
......@@ -727,9 +745,9 @@ reg_ch5ltsthr
CH5LTSTHR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x25
0x26
</td>
<td >
REG
......@@ -744,9 +762,9 @@ reg_ch6ltscyr
CH6LTSCYR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x26
0x27
</td>
<td >
REG
......@@ -761,9 +779,9 @@ reg_ch6ltstlr
CH6LTSTLR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x27
0x28
</td>
<td >
REG
......@@ -778,9 +796,9 @@ reg_ch6ltsthr
CH6LTSTHR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x28
0x29
</td>
<td >
REG
......@@ -795,9 +813,9 @@ reg_lsr
LSR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x29
0x2a
</td>
<td >
REG
......@@ -812,9 +830,9 @@ reg_oswr
OSWR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x2a
0x2b
</td>
<td >
REG
......@@ -829,9 +847,9 @@ reg_uidlr
UIDLR
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x2b
0x2c
</td>
<td >
REG
......@@ -846,9 +864,9 @@ reg_uidhr
UIDHR
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x2c
0x2d
</td>
<td >
REG
......@@ -997,10 +1015,10 @@ wb_stb_i
</td>
<td class="td_pblock_right">
reg_sr_i2c_wdto_o
reg_sr_hwvers_i[3:0]
</td>
<td class="td_arrow_right">
&rarr;
&lArr;
</td>
</tr>
<tr>
......@@ -1014,7 +1032,7 @@ wb_we_i
</td>
<td class="td_pblock_right">
reg_sr_i2c_wdto_i
reg_sr_wrpres_i
</td>
<td class="td_arrow_right">
&larr;
......@@ -1028,13 +1046,13 @@ reg_sr_i2c_wdto_i
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
reg_sr_i2c_wdto_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
......@@ -1048,10 +1066,10 @@ wb_stall_o
</td>
<td class="td_pblock_right">
reg_sr_wrpres_i
<b>ERR:</b>
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
......@@ -1065,7 +1083,7 @@ reg_sr_wrpres_i
</td>
<td class="td_pblock_right">
reg_sr_i2c_err_o
reg_err_i2c_wdto_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1082,7 +1100,7 @@ reg_sr_i2c_err_o
</td>
<td class="td_pblock_right">
reg_sr_i2c_err_i
reg_err_i2c_wdto_i
</td>
<td class="td_arrow_right">
&larr;
......@@ -1099,7 +1117,7 @@ reg_sr_i2c_err_i
</td>
<td class="td_pblock_right">
reg_sr_i2c_err_load_o
reg_err_i2c_wdto_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1116,10 +1134,10 @@ reg_sr_i2c_err_load_o
</td>
<td class="td_pblock_right">
reg_sr_pmisse_o[5:0]
reg_err_i2c_err_o
</td>
<td class="td_arrow_right">
&rArr;
&rarr;
</td>
</tr>
<tr>
......@@ -1133,10 +1151,10 @@ reg_sr_pmisse_o[5:0]
</td>
<td class="td_pblock_right">
reg_sr_pmisse_i[5:0]
reg_err_i2c_err_i
</td>
<td class="td_arrow_right">
&lArr;
&larr;
</td>
</tr>
<tr>
......@@ -1150,7 +1168,7 @@ reg_sr_pmisse_i[5:0]
</td>
<td class="td_pblock_right">
reg_sr_pmisse_load_o
reg_err_i2c_err_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1164,13 +1182,13 @@ reg_sr_pmisse_load_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
reg_err_flim_pmisse_o[5:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1184,10 +1202,10 @@ reg_sr_pmisse_load_o
</td>
<td class="td_pblock_right">
<b>CR:</b>
reg_err_flim_pmisse_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -1201,7 +1219,7 @@ reg_sr_pmisse_load_o
</td>
<td class="td_pblock_right">
reg_cr_rst_unlock_o
reg_err_flim_pmisse_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1218,10 +1236,10 @@ reg_cr_rst_unlock_o
</td>
<td class="td_pblock_right">
reg_cr_rst_unlock_i
reg_err_fwdg_pmisse_o[5:0]
</td>
<td class="td_arrow_right">
&larr;
&rArr;
</td>
</tr>
<tr>
......@@ -1235,10 +1253,10 @@ reg_cr_rst_unlock_i
</td>
<td class="td_pblock_right">
reg_cr_rst_unlock_load_o
reg_err_fwdg_pmisse_i[5:0]
</td>
<td class="td_arrow_right">
&rarr;
&lArr;
</td>
</tr>
<tr>
......@@ -1252,7 +1270,7 @@ reg_cr_rst_unlock_load_o
</td>
<td class="td_pblock_right">
reg_cr_rst_o
reg_err_fwdg_pmisse_load_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1266,13 +1284,13 @@ reg_cr_rst_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
reg_cr_rst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
......@@ -1286,10 +1304,10 @@ reg_cr_rst_i
</td>
<td class="td_pblock_right">
reg_cr_rst_load_o
<b>CR:</b>
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
......@@ -1303,10 +1321,10 @@ reg_cr_rst_load_o
</td>
<td class="td_pblock_right">
reg_cr_mpt_o[7:0]
reg_cr_rst_unlock_o
</td>
<td class="td_arrow_right">
&rArr;
&rarr;
</td>
</tr>
<tr>
......@@ -1320,10 +1338,10 @@ reg_cr_mpt_o[7:0]
</td>
<td class="td_pblock_right">
reg_cr_mpt_wr_o
reg_cr_rst_unlock_i
</td>
<td class="td_arrow_right">
&rarr;
&larr;
</td>
</tr>
<tr>
......@@ -1334,13 +1352,13 @@ reg_cr_mpt_wr_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
reg_cr_rst_unlock_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
......@@ -1354,10 +1372,10 @@ reg_cr_mpt_wr_o
</td>
<td class="td_pblock_right">
<b>CH1TTLPCR:</b>
reg_cr_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
......@@ -1371,10 +1389,10 @@ reg_cr_mpt_wr_o
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_o[31:0]
reg_cr_rst_i
</td>
<td class="td_arrow_right">
&rArr;
&larr;
</td>
</tr>
<tr>
......@@ -1388,10 +1406,10 @@ reg_ch1ttlpcr_o[31:0]
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_i[31:0]
reg_cr_rst_load_o
</td>
<td class="td_arrow_right">
&lArr;
&rarr;
</td>
</tr>
<tr>
......@@ -1405,10 +1423,10 @@ reg_ch1ttlpcr_i[31:0]
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_load_o
reg_cr_mpt_o[7:0]
</td>
<td class="td_arrow_right">
&rarr;
&rArr;
</td>
</tr>
<tr>
......@@ -1419,10 +1437,112 @@ reg_ch1ttlpcr_load_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
reg_cr_mpt_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>CH1TTLPCR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
reg_ch1ttlpcr_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
......@@ -2576,6 +2696,23 @@ reg_tbmr_chan_i[5:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
reg_tb_rd_req_p_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
reg_tbmr_wrtag_i
......@@ -4566,11 +4703,74 @@ Status Register
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
PMISSE[5:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_ERR
WRPRES
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
HWVERS[3:2]
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
HWVERS[1:0]
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
RTM[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
......@@ -4578,14 +4778,228 @@ I2C_ERR
<td >
</td>
<td >
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWITCHES[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GWVERS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
GWVERS
</b>[<i>read-only</i>]: Gateware version
<br>Leftmost nibble hex value is major release decimal value <br> Rightmost nibble hex value is minor release decimal value <br> e.g. <br> 0x11 -- v1.1 <br> 0x2e -- v2.14
<li><b>
SWITCHES
</b>[<i>read-only</i>]: Status of on-board general-purpose switches
<br>1 -- switch is ON <br> 0 -- switch is OFF
<li><b>
RTM
</b>[<i>read-only</i>]: RTM detection lines~\cite{rtm-det}
<br>1 -- line active <br> 0 -- line inactive
<li><b>
HWVERS
</b>[<i>read-only</i>]: Hardware version
<br>PCB version - Hardwired on the board <br> Only meaningful for HW v4 and over <br> Earlier versions show 0 <br> e.g. <br> 0x04 -- hw v4 <br> 0x05 -- hw v5 <br> 0x00 -- hw v3 and earlier
<li><b>
WRPRES
</b>[<i>read-only</i>]: White Rabbit present
<br>1 -- White Rabbit present <br> 0 -- White Rabbit not present
</ul>
<a name="ERR"></a>
<h3><a name="sect_3_3">3.3. ERR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
reg_err
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ERR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Error Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4617,29 +5031,29 @@ I2C_ERR
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRPRES
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_WDTO
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
RTM[5:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -4671,14 +5085,14 @@ RTM[5:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWITCHES[7:0]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=6 class="td_field">
FWDG_PMISSE[5:0]
</td>
<td >
......@@ -4725,14 +5139,14 @@ SWITCHES[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GWVERS[7:0]
<td style="border: solid 1px black;" colspan=6 class="td_field">
FLIM_PMISSE[5:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_ERR
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_WDTO
</td>
<td >
......@@ -4753,36 +5167,24 @@ GWVERS[7:0]
</table>
<ul>
<li><b>
GWVERS
</b>[<i>read-only</i>]: Gateware version
<br>Leftmost nibble hex value is major release decimal value <br> Rightmost nibble hex value is minor release decimal value <br> e.g. <br> 0x11 -- v1.1 <br> 0x2e -- v2.14
<li><b>
SWITCHES
</b>[<i>read-only</i>]: Status of on-board general-purpose switches
<br>1 -- switch is ON <br> 0 -- switch is OFF
<li><b>
RTM
</b>[<i>read-only</i>]: RTM detection lines~\cite{rtm-det}
<br>1 -- line active <br> 0 -- line inactive
<li><b>
I2C_WDTO
</b>[<i>read/write</i>]: I2C communication watchdog timeout error
<br>1 -- timeout occured <br> 0 -- no timeout <br> This bit can be cleared by writing a '1' to it
<li><b>
WRPRES
</b>[<i>read-only</i>]: White Rabbit present
<br>1 -- White Rabbit present <br> 0 -- White Rabbit not present
<li><b>
I2C_ERR
</b>[<i>read/write</i>]: I2C communication error
<br>1 -- attempted to address non-existing address <br> 0 -- idle <br> This bit can be cleared by writing a '1' to it
<li><b>
PMISSE
</b>[<i>read/write</i>]: Pulse missed error
<br>1 -- pulse arrived during pulse rejection phase <br> 0 -- idle <br> Bit 0 -- channel 1 <br> Bit 1 -- channel 2 <br> etc. <br> Each bit can be cleared by writing a '1' to it
FLIM_PMISSE
</b>[<i>read/write</i>]: Frequency error
<br>1 -- Input above maximum supported frequency <br> 0 -- idle <br> Bit 0 -- channel 1 <br> Bit 1 -- channel 2 <br> etc. <br> Each bit can be cleared by writing a '1' to it
<li><b>
FWDG_PMISSE
</b>[<i>read/write</i>]: Frequency watchdog error
<br>1 -- Pulse over maximum pulse count for given frequency' <br> 0 -- idle <br> Bit 0 -- channel 1 <br> Bit 1 -- channel 2 <br> etc. <br> Each bit can be cleared by writing a '1' to it
</ul>
<a name="CR"></a>
<h3><a name="sect_3_3">3.3. CR</a></h3>
<h3><a name="sect_3_4">3.4. CR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4797,7 +5199,7 @@ reg_cr
<b>HW address: </b>
</td>
<td class="td_code">
0x2
0x3
</td>
</tr>
<tr>
......@@ -4813,7 +5215,7 @@ CR
<b>C offset: </b>
</td>
<td class="td_code">
0x8
0xc
</td>
</tr>
</table>
......@@ -5051,7 +5453,7 @@ MPT
<br>Write the following sequence to trigger a pulse: <br> 0xde -- Byte 1 of magic sequence <br> 0xad -- Byte 2 of magic sequence <br> 0xbe -- Byte 3 of magic sequence <br> 0xef -- Byte 4 of magic sequence <br> Number in range 1..6 -- trigger a pulse
</ul>
<a name="CH1TTLPCR"></a>
<h3><a name="sect_3_4">3.4. CH1TTLPCR</a></h3>
<h3><a name="sect_3_5">3.5. CH1TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5066,7 +5468,7 @@ reg_ch1ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x3
0x4
</td>
</tr>
<tr>
......@@ -5082,7 +5484,7 @@ CH1TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0xc
0x10
</td>
</tr>
</table>
......@@ -5311,7 +5713,7 @@ CH1TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH2TTLPCR"></a>
<h3><a name="sect_3_5">3.5. CH2TTLPCR</a></h3>
<h3><a name="sect_3_6">3.6. CH2TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5326,7 +5728,7 @@ reg_ch2ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x4
0x5
</td>
</tr>
<tr>
......@@ -5342,7 +5744,7 @@ CH2TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x10
0x14
</td>
</tr>
</table>
......@@ -5571,7 +5973,7 @@ CH2TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH3TTLPCR"></a>
<h3><a name="sect_3_6">3.6. CH3TTLPCR</a></h3>
<h3><a name="sect_3_7">3.7. CH3TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5586,7 +5988,7 @@ reg_ch3ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x5
0x6
</td>
</tr>
<tr>
......@@ -5602,7 +6004,7 @@ CH3TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x14
0x18
</td>
</tr>
</table>
......@@ -5831,7 +6233,7 @@ CH3TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH4TTLPCR"></a>
<h3><a name="sect_3_7">3.7. CH4TTLPCR</a></h3>
<h3><a name="sect_3_8">3.8. CH4TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -5846,7 +6248,7 @@ reg_ch4ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x6
0x7
</td>
</tr>
<tr>
......@@ -5862,7 +6264,7 @@ CH4TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x18
0x1c
</td>
</tr>
</table>
......@@ -6091,7 +6493,7 @@ CH4TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH5TTLPCR"></a>
<h3><a name="sect_3_8">3.8. CH5TTLPCR</a></h3>
<h3><a name="sect_3_9">3.9. CH5TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6106,7 +6508,7 @@ reg_ch5ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x7
0x8
</td>
</tr>
<tr>
......@@ -6122,7 +6524,7 @@ CH5TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
0x20
</td>
</tr>
</table>
......@@ -6351,7 +6753,7 @@ CH5TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH6TTLPCR"></a>
<h3><a name="sect_3_9">3.9. CH6TTLPCR</a></h3>
<h3><a name="sect_3_10">3.10. CH6TTLPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6366,7 +6768,7 @@ reg_ch6ttlpcr
<b>HW address: </b>
</td>
<td class="td_code">
0x8
0x9
</td>
</tr>
<tr>
......@@ -6382,7 +6784,7 @@ CH6TTLPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x20
0x24
</td>
</tr>
</table>
......@@ -6611,7 +7013,7 @@ CH6TTLPCR
</b>[<i>read/write</i>]: TTL pulse counter value
</ul>
<a name="CH1BLOPCR"></a>
<h3><a name="sect_3_10">3.10. CH1BLOPCR</a></h3>
<h3><a name="sect_3_11">3.11. CH1BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6626,7 +7028,7 @@ reg_ch1blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0x9
0xa
</td>
</tr>
<tr>
......@@ -6642,7 +7044,7 @@ CH1BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x24
0x28
</td>
</tr>
</table>
......@@ -6871,7 +7273,7 @@ CH1BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="CH2BLOPCR"></a>
<h3><a name="sect_3_11">3.11. CH2BLOPCR</a></h3>
<h3><a name="sect_3_12">3.12. CH2BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -6886,7 +7288,7 @@ reg_ch2blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0xa
0xb
</td>
</tr>
<tr>
......@@ -6902,7 +7304,7 @@ CH2BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x28
0x2c
</td>
</tr>
</table>
......@@ -7131,7 +7533,7 @@ CH2BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="CH3BLOPCR"></a>
<h3><a name="sect_3_12">3.12. CH3BLOPCR</a></h3>
<h3><a name="sect_3_13">3.13. CH3BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -7146,7 +7548,7 @@ reg_ch3blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0xb
0xc
</td>
</tr>
<tr>
......@@ -7162,7 +7564,7 @@ CH3BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
0x30
</td>
</tr>
</table>
......@@ -7391,7 +7793,7 @@ CH3BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="CH4BLOPCR"></a>
<h3><a name="sect_3_13">3.13. CH4BLOPCR</a></h3>
<h3><a name="sect_3_14">3.14. CH4BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -7406,7 +7808,7 @@ reg_ch4blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0xc
0xd
</td>
</tr>
<tr>
......@@ -7422,7 +7824,7 @@ CH4BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x30
0x34
</td>
</tr>
</table>
......@@ -7651,7 +8053,7 @@ CH4BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="CH5BLOPCR"></a>
<h3><a name="sect_3_14">3.14. CH5BLOPCR</a></h3>
<h3><a name="sect_3_15">3.15. CH5BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -7666,7 +8068,7 @@ reg_ch5blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0xd
0xe
</td>
</tr>
<tr>
......@@ -7682,7 +8084,7 @@ CH5BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x34
0x38
</td>
</tr>
</table>
......@@ -7911,7 +8313,7 @@ CH5BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="CH6BLOPCR"></a>
<h3><a name="sect_3_15">3.15. CH6BLOPCR</a></h3>
<h3><a name="sect_3_16">3.16. CH6BLOPCR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -7926,7 +8328,7 @@ reg_ch6blopcr
<b>HW address: </b>
</td>
<td class="td_code">
0xe
0xf
</td>
</tr>
<tr>
......@@ -7942,7 +8344,7 @@ CH6BLOPCR
<b>C offset: </b>
</td>
<td class="td_code">
0x38
0x3c
</td>
</tr>
</table>
......@@ -8171,7 +8573,7 @@ CH6BLOPCR
</b>[<i>read/write</i>]: BLO pulse counter value
</ul>
<a name="TVLR"></a>
<h3><a name="sect_3_16">3.16. TVLR</a></h3>
<h3><a name="sect_3_17">3.17. TVLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8186,7 +8588,7 @@ reg_tvlr
<b>HW address: </b>
</td>
<td class="td_code">
0xf
0x10
</td>
</tr>
<tr>
......@@ -8202,7 +8604,7 @@ TVLR
<b>C offset: </b>
</td>
<td class="td_code">
0x3c
0x40
</td>
</tr>
</table>
......@@ -8432,7 +8834,7 @@ TVLR
<br>Writing this field resets the internal cycles counter.
</ul>
<a name="TVHR"></a>
<h3><a name="sect_3_17">3.17. TVHR</a></h3>
<h3><a name="sect_3_18">3.18. TVHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8447,7 +8849,7 @@ reg_tvhr
<b>HW address: </b>
</td>
<td class="td_code">
0x10
0x11
</td>
</tr>
<tr>
......@@ -8463,7 +8865,7 @@ TVHR
<b>C offset: </b>
</td>
<td class="td_code">
0x40
0x44
</td>
</tr>
</table>
......@@ -8693,7 +9095,7 @@ TVHR
<br>Writing this field resets the internal cycles counter.
</ul>
<a name="TBMR"></a>
<h3><a name="sect_3_18">3.18. TBMR</a></h3>
<h3><a name="sect_3_19">3.19. TBMR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8708,7 +9110,7 @@ reg_tbmr
<b>HW address: </b>
</td>
<td class="td_code">
0x11
0x12
</td>
</tr>
<tr>
......@@ -8724,7 +9126,7 @@ TBMR
<b>C offset: </b>
</td>
<td class="td_code">
0x44
0x48
</td>
</tr>
</table>
......@@ -8958,7 +9360,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="TBCYR"></a>
<h3><a name="sect_3_19">3.19. TBCYR</a></h3>
<h3><a name="sect_3_20">3.20. TBCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -8973,7 +9375,7 @@ reg_tbcyr
<b>HW address: </b>
</td>
<td class="td_code">
0x12
0x13
</td>
</tr>
<tr>
......@@ -8989,7 +9391,7 @@ TBCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x48
0x4c
</td>
</tr>
</table>
......@@ -9219,7 +9621,7 @@ TBCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="TBTLR"></a>
<h3><a name="sect_3_20">3.20. TBTLR</a></h3>
<h3><a name="sect_3_21">3.21. TBTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9234,7 +9636,7 @@ reg_tbtlr
<b>HW address: </b>
</td>
<td class="td_code">
0x13
0x14
</td>
</tr>
<tr>
......@@ -9250,7 +9652,7 @@ TBTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x4c
0x50
</td>
</tr>
</table>
......@@ -9480,7 +9882,7 @@ TBTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="TBTHR"></a>
<h3><a name="sect_3_21">3.21. TBTHR</a></h3>
<h3><a name="sect_3_22">3.22. TBTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9495,7 +9897,7 @@ reg_tbthr
<b>HW address: </b>
</td>
<td class="td_code">
0x14
0x15
</td>
</tr>
<tr>
......@@ -9511,7 +9913,7 @@ TBTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x50
0x54
</td>
</tr>
</table>
......@@ -9741,7 +10143,7 @@ TBTHR
<br>Value of the TAI seconds counter bits 39..32 when time tag was taken.
</ul>
<a name="TBCSR"></a>
<h3><a name="sect_3_22">3.22. TBCSR</a></h3>
<h3><a name="sect_3_23">3.23. TBCSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -9756,7 +10158,7 @@ reg_tbcsr
<b>HW address: </b>
</td>
<td class="td_code">
0x15
0x16
</td>
</tr>
<tr>
......@@ -9772,7 +10174,7 @@ TBCSR
<b>C offset: </b>
</td>
<td class="td_code">
0x54
0x58
</td>
</tr>
</table>
......@@ -10014,7 +10416,7 @@ CLR
<br>1 -- clear<br> 0 -- no effect
</ul>
<a name="CH1LTSCYR"></a>
<h3><a name="sect_3_23">3.23. CH1LTSCYR</a></h3>
<h3><a name="sect_3_24">3.24. CH1LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10029,7 +10431,7 @@ reg_ch1ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x16
0x17
</td>
</tr>
<tr>
......@@ -10045,7 +10447,7 @@ CH1LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x58
0x5c
</td>
</tr>
</table>
......@@ -10275,7 +10677,7 @@ CH1LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH1LTSTLR"></a>
<h3><a name="sect_3_24">3.24. CH1LTSTLR</a></h3>
<h3><a name="sect_3_25">3.25. CH1LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10290,7 +10692,7 @@ reg_ch1ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x17
0x18
</td>
</tr>
<tr>
......@@ -10306,7 +10708,7 @@ CH1LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x5c
0x60
</td>
</tr>
</table>
......@@ -10536,7 +10938,7 @@ CH1LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH1LTSTHR"></a>
<h3><a name="sect_3_25">3.25. CH1LTSTHR</a></h3>
<h3><a name="sect_3_26">3.26. CH1LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10551,7 +10953,7 @@ reg_ch1ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x18
0x19
</td>
</tr>
<tr>
......@@ -10567,7 +10969,7 @@ CH1LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x60
0x64
</td>
</tr>
</table>
......@@ -10801,7 +11203,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="CH2LTSCYR"></a>
<h3><a name="sect_3_26">3.26. CH2LTSCYR</a></h3>
<h3><a name="sect_3_27">3.27. CH2LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10816,7 +11218,7 @@ reg_ch2ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x19
0x1a
</td>
</tr>
<tr>
......@@ -10832,7 +11234,7 @@ CH2LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x64
0x68
</td>
</tr>
</table>
......@@ -11062,7 +11464,7 @@ CH2LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH2LTSTLR"></a>
<h3><a name="sect_3_27">3.27. CH2LTSTLR</a></h3>
<h3><a name="sect_3_28">3.28. CH2LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11077,7 +11479,7 @@ reg_ch2ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x1a
0x1b
</td>
</tr>
<tr>
......@@ -11093,7 +11495,7 @@ CH2LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x68
0x6c
</td>
</tr>
</table>
......@@ -11323,7 +11725,7 @@ CH2LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH2LTSTHR"></a>
<h3><a name="sect_3_28">3.28. CH2LTSTHR</a></h3>
<h3><a name="sect_3_29">3.29. CH2LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11338,7 +11740,7 @@ reg_ch2ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x1b
0x1c
</td>
</tr>
<tr>
......@@ -11354,7 +11756,7 @@ CH2LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x6c
0x70
</td>
</tr>
</table>
......@@ -11588,7 +11990,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="CH3LTSCYR"></a>
<h3><a name="sect_3_29">3.29. CH3LTSCYR</a></h3>
<h3><a name="sect_3_30">3.30. CH3LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11603,7 +12005,7 @@ reg_ch3ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x1c
0x1d
</td>
</tr>
<tr>
......@@ -11619,7 +12021,7 @@ CH3LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x70
0x74
</td>
</tr>
</table>
......@@ -11849,7 +12251,7 @@ CH3LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH3LTSTLR"></a>
<h3><a name="sect_3_30">3.30. CH3LTSTLR</a></h3>
<h3><a name="sect_3_31">3.31. CH3LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11864,7 +12266,7 @@ reg_ch3ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x1d
0x1e
</td>
</tr>
<tr>
......@@ -11880,7 +12282,7 @@ CH3LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x74
0x78
</td>
</tr>
</table>
......@@ -12110,7 +12512,7 @@ CH3LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH3LTSTHR"></a>
<h3><a name="sect_3_31">3.31. CH3LTSTHR</a></h3>
<h3><a name="sect_3_32">3.32. CH3LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12125,7 +12527,7 @@ reg_ch3ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x1e
0x1f
</td>
</tr>
<tr>
......@@ -12141,7 +12543,7 @@ CH3LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x78
0x7c
</td>
</tr>
</table>
......@@ -12375,7 +12777,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="CH4LTSCYR"></a>
<h3><a name="sect_3_32">3.32. CH4LTSCYR</a></h3>
<h3><a name="sect_3_33">3.33. CH4LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12390,7 +12792,7 @@ reg_ch4ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x1f
0x20
</td>
</tr>
<tr>
......@@ -12406,7 +12808,7 @@ CH4LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x7c
0x80
</td>
</tr>
</table>
......@@ -12636,7 +13038,7 @@ CH4LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH4LTSTLR"></a>
<h3><a name="sect_3_33">3.33. CH4LTSTLR</a></h3>
<h3><a name="sect_3_34">3.34. CH4LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12651,7 +13053,7 @@ reg_ch4ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x20
0x21
</td>
</tr>
<tr>
......@@ -12667,7 +13069,7 @@ CH4LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x80
0x84
</td>
</tr>
</table>
......@@ -12897,7 +13299,7 @@ CH4LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH4LTSTHR"></a>
<h3><a name="sect_3_34">3.34. CH4LTSTHR</a></h3>
<h3><a name="sect_3_35">3.35. CH4LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12912,7 +13314,7 @@ reg_ch4ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x21
0x22
</td>
</tr>
<tr>
......@@ -12928,7 +13330,7 @@ CH4LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x84
0x88
</td>
</tr>
</table>
......@@ -13162,7 +13564,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="CH5LTSCYR"></a>
<h3><a name="sect_3_35">3.35. CH5LTSCYR</a></h3>
<h3><a name="sect_3_36">3.36. CH5LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13177,7 +13579,7 @@ reg_ch5ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x22
0x23
</td>
</tr>
<tr>
......@@ -13193,7 +13595,7 @@ CH5LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x88
0x8c
</td>
</tr>
</table>
......@@ -13423,7 +13825,7 @@ CH5LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH5LTSTLR"></a>
<h3><a name="sect_3_36">3.36. CH5LTSTLR</a></h3>
<h3><a name="sect_3_37">3.37. CH5LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13438,7 +13840,7 @@ reg_ch5ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x23
0x24
</td>
</tr>
<tr>
......@@ -13454,7 +13856,7 @@ CH5LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x8c
0x90
</td>
</tr>
</table>
......@@ -13684,7 +14086,7 @@ CH5LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH5LTSTHR"></a>
<h3><a name="sect_3_37">3.37. CH5LTSTHR</a></h3>
<h3><a name="sect_3_38">3.38. CH5LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13699,7 +14101,7 @@ reg_ch5ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x24
0x25
</td>
</tr>
<tr>
......@@ -13715,7 +14117,7 @@ CH5LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x90
0x94
</td>
</tr>
</table>
......@@ -13949,7 +14351,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="CH6LTSCYR"></a>
<h3><a name="sect_3_38">3.38. CH6LTSCYR</a></h3>
<h3><a name="sect_3_39">3.39. CH6LTSCYR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13964,7 +14366,7 @@ reg_ch6ltscyr
<b>HW address: </b>
</td>
<td class="td_code">
0x25
0x26
</td>
</tr>
<tr>
......@@ -13980,7 +14382,7 @@ CH6LTSCYR
<b>C offset: </b>
</td>
<td class="td_code">
0x94
0x98
</td>
</tr>
</table>
......@@ -14210,7 +14612,7 @@ CH6LTSCYR
<br>Value of the 8-ns cycles counter when time tag was taken.
</ul>
<a name="CH6LTSTLR"></a>
<h3><a name="sect_3_39">3.39. CH6LTSTLR</a></h3>
<h3><a name="sect_3_40">3.40. CH6LTSTLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -14225,7 +14627,7 @@ reg_ch6ltstlr
<b>HW address: </b>
</td>
<td class="td_code">
0x26
0x27
</td>
</tr>
<tr>
......@@ -14241,7 +14643,7 @@ CH6LTSTLR
<b>C offset: </b>
</td>
<td class="td_code">
0x98
0x9c
</td>
</tr>
</table>
......@@ -14471,7 +14873,7 @@ CH6LTSTLR
<br>Value of the TAI seconds counter bits 31..0 when time tag was taken.
</ul>
<a name="CH6LTSTHR"></a>
<h3><a name="sect_3_40">3.40. CH6LTSTHR</a></h3>
<h3><a name="sect_3_41">3.41. CH6LTSTHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -14486,7 +14888,7 @@ reg_ch6ltsthr
<b>HW address: </b>
</td>
<td class="td_code">
0x27
0x28
</td>
</tr>
<tr>
......@@ -14502,7 +14904,7 @@ CH6LTSTHR
<b>C offset: </b>
</td>
<td class="td_code">
0x9c
0xa0
</td>
</tr>
</table>
......@@ -14736,7 +15138,7 @@ WRTAG
<br>1 - Current time tag generated with White Rabbit <br> 0 - Current time tag generated with internal counter
</ul>
<a name="LSR"></a>
<h3><a name="sect_3_41">3.41. LSR</a></h3>
<h3><a name="sect_3_42">3.42. LSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -14751,7 +15153,7 @@ reg_lsr
<b>HW address: </b>
</td>
<td class="td_code">
0x28
0x29
</td>
</tr>
<tr>
......@@ -14767,7 +15169,7 @@ LSR
<b>C offset: </b>
</td>
<td class="td_code">
0xa0
0xa4
</td>
</tr>
</table>
......@@ -15017,7 +15419,7 @@ REARFS
<br>High if line is in failsafe mode (e.g., no cable plugged in)<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
</ul>
<a name="OSWR"></a>
<h3><a name="sect_3_42">3.42. OSWR</a></h3>
<h3><a name="sect_3_43">3.43. OSWR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -15032,7 +15434,7 @@ reg_oswr
<b>HW address: </b>
</td>
<td class="td_code">
0x29
0x2a
</td>
</tr>
<tr>
......@@ -15048,7 +15450,7 @@ OSWR
<b>C offset: </b>
</td>
<td class="td_code">
0xa4
0xa8
</td>
</tr>
</table>
......@@ -15278,7 +15680,7 @@ SWITCHES
<br>1 -- switch is ON <br> 0 -- switch is OFF
</ul>
<a name="UIDLR"></a>
<h3><a name="sect_3_43">3.43. UIDLR</a></h3>
<h3><a name="sect_3_44">3.44. UIDLR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -15293,7 +15695,7 @@ reg_uidlr
<b>HW address: </b>
</td>
<td class="td_code">
0x2a
0x2b
</td>
</tr>
<tr>
......@@ -15309,7 +15711,7 @@ UIDLR
<b>C offset: </b>
</td>
<td class="td_code">
0xa8
0xac
</td>
</tr>
</table>
......@@ -15538,7 +15940,7 @@ UIDLR
</b>[<i>read-only</i>]: LS bits of 1-wire DS18B20U thermometer ID
</ul>
<a name="UIDHR"></a>
<h3><a name="sect_3_44">3.44. UIDHR</a></h3>
<h3><a name="sect_3_45">3.45. UIDHR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -15553,7 +15955,7 @@ reg_uidhr
<b>HW address: </b>
</td>
<td class="td_code">
0x2b
0x2c
</td>
</tr>
<tr>
......@@ -15569,7 +15971,7 @@ UIDHR
<b>C offset: </b>
</td>
<td class="td_code">
0xac
0xb0
</td>
</tr>
</table>
......@@ -15798,7 +16200,7 @@ UIDHR
</b>[<i>read-only</i>]: MS bits of 1-wire DS18B20U thermometer ID
</ul>
<a name="TEMPR"></a>
<h3><a name="sect_3_45">3.45. TEMPR</a></h3>
<h3><a name="sect_3_46">3.46. TEMPR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -15813,7 +16215,7 @@ reg_tempr
<b>HW address: </b>
</td>
<td class="td_code">
0x2c
0x2d
</td>
</tr>
<tr>
......@@ -15829,7 +16231,7 @@ TEMPR
<b>C offset: </b>
</td>
<td class="td_code">
0xb0
0xb4
</td>
</tr>
</table>
......
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : .\conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : 12/20/16 14:58:27
-- Author : auto-generated by wbgen2 from .\conv_regs.wb
-- Created : 02/01/17 15:43:00
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -35,20 +35,26 @@ entity conv_regs is
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i : in std_logic_vector(3 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic_vector(5 downto 0);
reg_sr_pmisse_i : in std_logic_vector(5 downto 0);
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_err_i2c_wdto_o : out std_logic;
reg_err_i2c_wdto_i : in std_logic;
reg_err_i2c_wdto_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_err_i2c_err_o : out std_logic;
reg_err_i2c_err_i : in std_logic;
reg_err_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_flim_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_flim_pmisse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -118,6 +124,7 @@ entity conv_regs is
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
reg_tb_rd_req_p_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
......@@ -236,9 +243,10 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_err_i2c_wdto_load_o <= '0';
reg_err_i2c_err_load_o <= '0';
reg_err_flim_pmisse_load_o <= '0';
reg_err_fwdg_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -256,6 +264,7 @@ begin
reg_ch6blopcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
reg_tbcsr_clr_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -263,9 +272,10 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_err_i2c_wdto_load_o <= '0';
reg_err_i2c_err_load_o <= '0';
reg_err_flim_pmisse_load_o <= '0';
reg_err_fwdg_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -283,12 +293,14 @@ begin
reg_ch6blopcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
reg_tbcsr_clr_load_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_err_i2c_wdto_load_o <= '0';
reg_err_i2c_err_load_o <= '0';
reg_err_flim_pmisse_load_o <= '0';
reg_err_fwdg_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -319,21 +331,51 @@ begin
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
reg_sr_i2c_err_load_o <= '1';
reg_sr_pmisse_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= reg_sr_i2c_err_i;
rddata_reg(30 downto 25) <= reg_sr_pmisse_i;
rddata_reg(25 downto 22) <= reg_sr_hwvers_i;
rddata_reg(26) <= reg_sr_wrpres_i;
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
reg_err_i2c_wdto_load_o <= '1';
reg_err_i2c_err_load_o <= '1';
reg_err_flim_pmisse_load_o <= '1';
reg_err_fwdg_pmisse_load_o <= '1';
end if;
rddata_reg(0) <= reg_err_i2c_wdto_i;
rddata_reg(1) <= reg_err_i2c_err_i;
rddata_reg(7 downto 2) <= reg_err_flim_pmisse_i;
rddata_reg(13 downto 8) <= reg_err_fwdg_pmisse_i;
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
reg_cr_rst_unlock_load_o <= '1';
reg_cr_rst_load_o <= '1';
......@@ -373,98 +415,98 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
when "000100" =>
if (wb_we_i = '1') then
reg_ch1ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
when "000101" =>
if (wb_we_i = '1') then
reg_ch2ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
when "000110" =>
if (wb_we_i = '1') then
reg_ch3ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
when "000111" =>
if (wb_we_i = '1') then
reg_ch4ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
when "001000" =>
if (wb_we_i = '1') then
reg_ch5ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
when "001001" =>
if (wb_we_i = '1') then
reg_ch6ttlpcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6ttlpcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
when "001010" =>
if (wb_we_i = '1') then
reg_ch1blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
when "001011" =>
if (wb_we_i = '1') then
reg_ch2blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
when "001100" =>
if (wb_we_i = '1') then
reg_ch3blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
when "001101" =>
if (wb_we_i = '1') then
reg_ch4blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
when "001110" =>
if (wb_we_i = '1') then
reg_ch5blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
when "001111" =>
if (wb_we_i = '1') then
reg_ch6blopcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6blopcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
when "010000" =>
if (wb_we_i = '1') then
reg_tvlr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_tvlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
when "010001" =>
if (wb_we_i = '1') then
reg_tvhr_load_o <= '1';
end if;
......@@ -495,10 +537,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
when "010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
reg_tb_rd_req_p_o <= '1';
rddata_reg(31) <= reg_tbmr_wrtag_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -527,7 +570,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
when "010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_tbcyr_i;
......@@ -537,13 +580,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
when "010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_tbtlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
when "010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_tbthr_i;
......@@ -573,7 +616,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
when "010110" =>
if (wb_we_i = '1') then
reg_tbcsr_clr_load_o <= '1';
end if;
......@@ -605,7 +648,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
when "010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch1ltscyr_i;
......@@ -615,13 +658,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
when "011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch1ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
when "011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch1ltsthr_tai_i;
......@@ -651,7 +694,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch2ltscyr_i;
......@@ -661,13 +704,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
when "011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch2ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
when "011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch2ltsthr_tai_i;
......@@ -697,7 +740,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch3ltscyr_i;
......@@ -707,13 +750,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
when "011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch3ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
when "011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch3ltsthr_tai_i;
......@@ -743,7 +786,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
when "100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch4ltscyr_i;
......@@ -753,13 +796,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
when "100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch4ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
when "100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch4ltsthr_tai_i;
......@@ -789,7 +832,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch5ltscyr_i;
......@@ -799,13 +842,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
when "100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch5ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch5ltsthr_tai_i;
......@@ -835,7 +878,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
when "100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch6ltscyr_i;
......@@ -845,13 +888,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
when "100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch6ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
when "101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch6ltsthr_tai_i;
......@@ -881,7 +924,7 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
when "101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= reg_lsr_front_i;
......@@ -892,25 +935,25 @@ begin
rddata_reg(31 downto 26) <= reg_lsr_rearfs_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101001" =>
when "101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_oswr_switches_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
when "101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_uidlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
when "101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_uidhr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
when "101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= reg_tempr_i;
......@@ -949,13 +992,16 @@ begin
-- Gateware version
-- Status of on-board general-purpose switches
-- RTM detection lines~\cite{rtm-det}
-- I2C communication watchdog timeout error
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- Hardware version
-- White Rabbit present
-- I2C communication watchdog timeout error
reg_err_i2c_wdto_o <= wrdata_reg(0);
-- I2C communication error
reg_sr_i2c_err_o <= wrdata_reg(24);
-- Pulse missed error
reg_sr_pmisse_o <= wrdata_reg(30 downto 25);
reg_err_i2c_err_o <= wrdata_reg(1);
-- Frequency error
reg_err_flim_pmisse_o <= wrdata_reg(7 downto 2);
-- Frequency watchdog error
reg_err_fwdg_pmisse_o <= wrdata_reg(13 downto 8);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit - active only if RST_UNLOCK is 1
......
......@@ -100,6 +100,37 @@ peripheral {
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Hardware version";
description = "PCB version - Hardwired on the board \
Only meaningful for HW v4 and over \
Earlier versions show 0 \
e.g. \
0x04 -- hw v4 \
0x05 -- hw v5 \
0x00 -- hw v3 and earlier";
prefix = "hwvers";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Error register
reg {
name = "ERR";
description = "Error Register";
prefix = "err";
field {
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
......@@ -112,15 +143,6 @@ peripheral {
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
......@@ -133,14 +155,29 @@ peripheral {
load = LOAD_EXT;
};
field {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \
name = "Frequency error";
description = "1 -- Input above maximum supported frequency \
0 -- idle \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "flim_pmisse";
type = SLV;
size = 6;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Frequency watchdog error";
description = "1 -- Pulse over maximum pulse count for given frequency' \
0 -- idle \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "pmisse";
prefix = "fwdg_pmisse";
type = SLV;
size = 6;
access_dev = READ_WRITE;
......@@ -149,7 +186,6 @@ peripheral {
};
};
-- Control Register
reg {
name = "CR";
......@@ -407,6 +443,7 @@ peripheral {
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
ack_read = "reg_tb_rd_req_p_o";
};
field {
name = "White Rabbit present";
......
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