removed references to common_components package

modules/genrams/Manifest.py

@@ -55,6 +55,9 @@ def __import_coregen_files():
 ##############################
 ## "Normal" manifest        ##
 ##############################
+
+print ("[genrams] target = " + target)
+
 if (target == "altera"):
 	modules = {"local" : "altera"}
 elif (target == "xilinx"):

modules/genrams/coregen_ip/blk_mem_gen_v4_1/Manifest.py

+files = [
+"blk_mem_gen_v4_1_xst_comp.vhd",
+"blk_mem_gen_v4_1_defaults.vhd",
+"blk_mem_gen_v4_1_pkg.vhd",
+"blk_mem_gen_getinit_pkg.vhd",
+"blk_mem_min_area_pkg.vhd",
+"blk_mem_gen_bindec.vhd",
+"blk_mem_gen_mux.vhd",
+"blk_mem_gen_prim_wrapper_s6.vhd",
+"blk_mem_gen_prim_wrapper_s6_init.vhd",
+"blk_mem_gen_prim_wrapper_s3adsp.vhd",
+"blk_mem_gen_prim_wrapper_s3adsp_init.vhd",
+"blk_mem_gen_prim_wrapper_s3a.vhd",
+"blk_mem_gen_prim_wrapper_s3a_init.vhd",
+"blk_mem_gen_prim_wrapper_v6.vhd",
+"blk_mem_gen_prim_wrapper_v6_init.vhd",
+"blk_mem_gen_prim_wrapper_v5.vhd",
+"blk_mem_gen_prim_wrapper_v5_init.vhd",
+"blk_mem_gen_prim_wrapper_v4.vhd",
+"blk_mem_gen_prim_wrapper_v4_init.vhd",
+"blk_mem_gen_prim_wrapper_s3.vhd",
+"blk_mem_gen_prim_wrapper_s3_init.vhd",
+"blk_mem_gen_prim_width.vhd",
+"blk_mem_gen_generic_cstr.vhd",
+"blk_mem_gen_ecc_encoder.vhd",
+"blk_mem_gen_ecc_decoder.vhd",
+"blk_mem_input_block.vhd",
+"blk_mem_output_block.vhd",
+"blk_mem_gen_top.vhd",
+"blk_mem_gen_v4_1_xst.vhd"]
+library = "blk_mem_gen_v4_1"