diff --git a/modules/genrams/Manifest.py b/modules/genrams/Manifest.py
index 5abc5c576862db8f29554e4402adee64e07b30f0..46403f38a1b56da38153c4d66b1a9f4321d32b4e 100644
--- a/modules/genrams/Manifest.py
+++ b/modules/genrams/Manifest.py
@@ -55,6 +55,9 @@ def __import_coregen_files():
##############################
## "Normal" manifest ##
##############################
+
+print ("[genrams] target = " + target)
+
if (target == "altera"):
modules = {"local" : "altera"}
elif (target == "xilinx"):
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/Manifest.py b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..7cad8578d5b9ac1be9cf3eb4a0cf5ea9f9faf3a3
--- /dev/null
+++ b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/Manifest.py
@@ -0,0 +1,31 @@
+files = [
+"blk_mem_gen_v4_1_xst_comp.vhd",
+"blk_mem_gen_v4_1_defaults.vhd",
+"blk_mem_gen_v4_1_pkg.vhd",
+"blk_mem_gen_getinit_pkg.vhd",
+"blk_mem_min_area_pkg.vhd",
+"blk_mem_gen_bindec.vhd",
+"blk_mem_gen_mux.vhd",
+"blk_mem_gen_prim_wrapper_s6.vhd",
+"blk_mem_gen_prim_wrapper_s6_init.vhd",
+"blk_mem_gen_prim_wrapper_s3adsp.vhd",
+"blk_mem_gen_prim_wrapper_s3adsp_init.vhd",
+"blk_mem_gen_prim_wrapper_s3a.vhd",
+"blk_mem_gen_prim_wrapper_s3a_init.vhd",
+"blk_mem_gen_prim_wrapper_v6.vhd",
+"blk_mem_gen_prim_wrapper_v6_init.vhd",
+"blk_mem_gen_prim_wrapper_v5.vhd",
+"blk_mem_gen_prim_wrapper_v5_init.vhd",
+"blk_mem_gen_prim_wrapper_v4.vhd",
+"blk_mem_gen_prim_wrapper_v4_init.vhd",
+"blk_mem_gen_prim_wrapper_s3.vhd",
+"blk_mem_gen_prim_wrapper_s3_init.vhd",
+"blk_mem_gen_prim_width.vhd",
+"blk_mem_gen_generic_cstr.vhd",
+"blk_mem_gen_ecc_encoder.vhd",
+"blk_mem_gen_ecc_decoder.vhd",
+"blk_mem_input_block.vhd",
+"blk_mem_output_block.vhd",
+"blk_mem_gen_top.vhd",
+"blk_mem_gen_v4_1_xst.vhd"]
+library = "blk_mem_gen_v4_1"
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ebac9550a19394efbc23885e85060a331a19659c
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..35fe9cd4d7cae47d31238fc79ebeba36dc9d9ece
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..50398bdcb4eb98a81e139492b232e9d2762d2ea0
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6800bffad27cbc8a4332969cc30c45f3efe06c02
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4d5bbbf4229125797b74975038b9f125f3ad045f
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..848aa4a681a9f6afe1e9a4b6b069153b9efb7de6
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c80ae56b9cce6058cc97ec4c18c431a0e438a80e
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8120bad22b84e9761ce67751022940331aa13224
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5ef5f3cff68e254bddb7df4cbe4d1f55f6c3eb13
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b16a9186378d3bcbdd4c2f36f35d6a5620bcaa92
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..70b2af014c7fd1be8e36273691f7cf0a374b519c
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1aeb519aa00b3539261f7399e34d0824098f0851
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a3e4c2b50bc16a18c827e2471efcc21e16987bd2
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7054cfe3d0df4c9af05a54ed20dcae4ddc1b6f30
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..172c201e8cbac2ac0967c7043f382f597adb4309
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1f36e5d2fc730ba8a87d05d3010cb43bb73e908c
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..73eb7b35ae1d5ffdd4c1e9f8d7c15dc38e593359
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..224f7973dd4d050b1d8509e3b7ba4e55831e0fd6
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..17e1fb097573c90cd9d152ab1a33cdf41475c02d
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..20ce4d08d6c0d7d4f19a0115475a87dc5b3c6daf
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f71bf31612408095745d88c2a12c2290900d89bd
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f4e6272dd98700f2b3d37f4d644d1086fc27f46b
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e4110ed9622ca5225b38046f977da000302b9ca
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..84f7775fad9b2f1164fe9d059b6da5d842e3b334
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d90aae731a330c554256ca5ddc61806887c6e078
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a73d4a370fdb3b22377d3a952b181ba0251bc42e
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..79bfbcb388e0c69f69d52384d8e06f0aa6031650
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b40b8538e0bc06063e73fba1c19cc23918656d48
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd differ
diff --git a/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a131749b81e33b2b7fe3f4e02b6ed315ab8a9bb6
Binary files /dev/null and b/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/Manifest.py b/modules/genrams/coregen_ip/fifo_generator_v6_1/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..d64a0f54ad4eea29df5fe32c0d48d54261d52f5a
--- /dev/null
+++ b/modules/genrams/coregen_ip/fifo_generator_v6_1/Manifest.py
@@ -0,0 +1,62 @@
+files = [
+"fifo_generator_v6_1_pkg.vhd",
+"fifo_generator_v6_1_defaults.vhd",
+"fifo_generator_v6_1_xst_comp.vhd",
+"input_blk.vhd",
+"output_blk.vhd",
+"shft_wrapper.vhd",
+"shft_ram.vhd",
+"dmem.vhd",
+"memory.vhd",
+"compare.vhd",
+"wr_bin_cntr.vhd",
+"rd_bin_cntr.vhd",
+"updn_cntr.vhd",
+"rd_status_flags_as.vhd",
+"rd_status_flags_ss.vhd",
+"rd_pe_as.vhd",
+"rd_pe_ss.vhd",
+"rd_handshaking_flags.vhd",
+"rd_dc_as.vhd",
+"rd_dc_fwft_ext_as.vhd",
+"dc_ss.vhd",
+"dc_ss_fwft.vhd",
+"rd_fwft.vhd",
+"rd_logic.vhd",
+"reset_blk_ramfifo.vhd",
+"clk_x_pntrs.vhd",
+"wr_status_flags_as.vhd",
+"wr_status_flags_ss.vhd",
+"wr_pf_as.vhd",
+"wr_pf_ss.vhd",
+"wr_handshaking_flags.vhd",
+"wr_dc_as.vhd",
+"wr_dc_fwft_ext_as.vhd",
+"wr_logic.vhd",
+"wr_status_flags_sshft.vhd",
+"rd_status_flags_sshft.vhd",
+"wr_pf_sshft.vhd",
+"rd_pe_sshft.vhd",
+"logic_sshft.vhd",
+"fifo_generator_ramfifo.vhd",
+"fifo_generator_v6_1_comps_builtin.vhd",
+"delay.vhd",
+"clk_x_pntrs_builtin.vhd",
+"bin_cntr.vhd",
+"logic_builtin.vhd",
+"reset_builtin.vhd",
+"builtin_prim.vhd",
+"builtin_extdepth.vhd",
+"builtin_top.vhd",
+"builtin_prim_v6.vhd",
+"builtin_extdepth_v6.vhd",
+"builtin_top_v6.vhd",
+"fifo_generator_v6_1_builtin.vhd",
+"rgtw.vhd",
+"wgtr.vhd",
+"input_block_fifo16_patch.vhd",
+"output_block_fifo16_patch.vhd",
+"fifo16_patch_top.vhd",
+"fifo_generator_v6_1_fifo16_patch.vhd",
+"fifo_generator_v6_1_xst.vhd"]
+library = "fifo_generator_v6_1"
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1533b05195d55fe062a15e7d18d89f9283e15e22
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f7dd8ebc104b3cbcd1e283526a7f7e064853b1d9
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b864d5189456180f4d356385866a9eeefc740c68
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0ff53596264d61f6b67a42cabc46f45884f3b781
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ef736229a45ae9b5e2a4ded297f65bbdf3415bd0
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..095cf6dc0bc5e55cb06dd5e9ea1cf50ba9ff66f4
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4a4066d7cabca8989c809bc895f7a321bd17e84a
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..79fddf71d95489c010d3ebe3eec86d4c78f1526a
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7e09bbe927f97e0810c3210bdda700ef451f2ae5
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd differ
diff --git a/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd b/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..89a19deda42ff264162e23e58170a6f2a6ca7ca5
Binary files /dev/null and b/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd differ
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diff --git a/modules/genrams/xilinx/generic_async_fifo.vhd b/modules/genrams/xilinx/generic_async_fifo.vhd
index 04e1dc454c1c3d9553424093ca7858485605e804..3c8e19c5395ee6e7f0eeb6853bfa31a59a70296b 100644
--- a/modules/genrams/xilinx/generic_async_fifo.vhd
+++ b/modules/genrams/xilinx/generic_async_fifo.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
--- Last update: 2011-03-25
+-- Last update: 2011-05-07
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -161,12 +161,12 @@ architecture syn of generic_async_fifo is
backup : in std_logic;
backup_marker : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
- prog_empty_thresh : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_empty_thresh_assert : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_empty_thresh_negate : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh_assert : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh_negate : in std_logic_vector(f_log2_size(g_size-1) downto 0);
+ prog_empty_thresh : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_empty_thresh_assert : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_empty_thresh_negate : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh_assert : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh_negate : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rd_rst : in std_logic;
@@ -180,7 +180,7 @@ architecture syn of generic_async_fifo is
injectsbiterr : in std_logic;
almost_empty : out std_logic;
almost_full : out std_logic;
- data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
empty : out std_logic;
full : out std_logic;
@@ -188,10 +188,10 @@ architecture syn of generic_async_fifo is
prog_empty : out std_logic;
prog_full : out std_logic;
valid : out std_logic;
- rd_data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ rd_data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
underflow : out std_logic;
wr_ack : out std_logic;
- wr_data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ wr_data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
sbiterr : out std_logic;
dbiterr : out std_logic);
end component;
diff --git a/modules/genrams/xilinx/generic_dpram.vhd b/modules/genrams/xilinx/generic_dpram.vhd
index 02e3ab8b5ddee0c025a0c0bcd292c1ac7556dd1f..3013293072fe2f816d4b6dacbe157b66fae8eb9f 100644
--- a/modules/genrams/xilinx/generic_dpram.vhd
+++ b/modules/genrams/xilinx/generic_dpram.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
--- Last update: 2011-04-10
+-- Last update: 2011-05-10
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -86,6 +86,9 @@ architecture syn of generic_dpram is
-- Takes parameters
-- filename : Name of the file from which to read data
+
+
+
impure function read_meminit_file(
filename : string
) return t_ram_type is
diff --git a/modules/genrams/xilinx/generic_sync_fifo.vhd b/modules/genrams/xilinx/generic_sync_fifo.vhd
index bf4accebf1829e12e547e7b7699b56505c72fc28..16b2be84dd196373ab06f71d9865f73a098fd8b5 100644
--- a/modules/genrams/xilinx/generic_sync_fifo.vhd
+++ b/modules/genrams/xilinx/generic_sync_fifo.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
--- Last update: 2011-03-25
+-- Last update: 2011-05-07
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -143,12 +143,12 @@ architecture syn of generic_sync_fifo is
backup : in std_logic;
backup_marker : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
- prog_empty_thresh : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_empty_thresh_assert : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_empty_thresh_negate : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh_assert : in std_logic_vector(f_log2_size(g_size-1) downto 0);
- prog_full_thresh_negate : in std_logic_vector(f_log2_size(g_size-1) downto 0);
+ prog_empty_thresh : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_empty_thresh_assert : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_empty_thresh_negate : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh_assert : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
+ prog_full_thresh_negate : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rd_rst : in std_logic;
@@ -162,7 +162,7 @@ architecture syn of generic_sync_fifo is
injectsbiterr : in std_logic;
almost_empty : out std_logic;
almost_full : out std_logic;
- data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
empty : out std_logic;
full : out std_logic;
@@ -170,10 +170,10 @@ architecture syn of generic_sync_fifo is
prog_empty : out std_logic;
prog_full : out std_logic;
valid : out std_logic;
- rd_data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ rd_data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
underflow : out std_logic;
wr_ack : out std_logic;
- wr_data_count : out std_logic_vector(f_log2_size(g_size-1) downto 0);
+ wr_data_count : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
sbiterr : out std_logic;
dbiterr : out std_logic);
end component;
diff --git a/modules/wishbone/wb_async_bridge/Manifest.py b/modules/wishbone/wb_async_bridge/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..da4fbcbdba01c4543c6301efe16a1c76d39da6a6
--- /dev/null
+++ b/modules/wishbone/wb_async_bridge/Manifest.py
@@ -0,0 +1 @@
+files = ["wb_cpu_bridge.vhd"]
diff --git a/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd b/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd
index 9062e13942a5d40a4a1f0dd007546e716498c654..c9f0f3eede38d8d8f683d313ab29c8e342120608 100644
--- a/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd
@@ -31,8 +31,9 @@ use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
+
+use work.gencores_pkg.all;
use work.wishbone_pkg.all;
-use work.common_components.all;
entity wb_cpu_bridge is
generic (
@@ -117,7 +118,7 @@ begin
gen_sync_chains_nosim : if(g_simulation = 0) generate
- sync_ffs_cs : sync_ffs
+ sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
@@ -128,7 +129,7 @@ begin
npulse_o => open
);
- sync_ffs_wr : sync_ffs
+ sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
@@ -139,7 +140,7 @@ begin
npulse_o => wr_pulse
);
- sync_ffs_rd : sync_ffs
+ sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
diff --git a/modules/wishbone/wb_gpio_port/Manifest.py b/modules/wishbone/wb_gpio_port/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..cd4aae4f47d29d26476e0b1ebf6f0a232f28ade5
--- /dev/null
+++ b/modules/wishbone/wb_gpio_port/Manifest.py
@@ -0,0 +1 @@
+files = ["wb_gpio_port.vhd"];
\ No newline at end of file
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 5f5ddbb490e0394ad8056f55cf92df25b34ac00a..0a5bf91cd4b369ba71b03c2f0b6fe8501f9e666c 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -26,7 +26,7 @@ use ieee.std_logic_arith.all;
library work;
use work.wishbone_pkg.all;
-use work.common_components.all;
+use work.gencores_pkg.all;
entity wb_gpio_port is
generic(g_num_pins : natural := 8 -- number of GPIO pins
@@ -71,7 +71,7 @@ begin
GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
- INPUT_SYNC : sync_ffs
+ INPUT_SYNC : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
diff --git a/modules/wishbone/wb_i2c_master/i2c_master_top.vhd b/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f1a63eddbd6b81521f614cdd7ba773c2db51d255
--- /dev/null
+++ b/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
@@ -0,0 +1,359 @@
+---------------------------------------------------------------------
+---- ----
+---- WISHBONE revB2 compl. I2C Master Core; top level ----
+---- ----
+---- ----
+---- Author: Richard Herveille ----
+---- richard@asics.ws ----
+---- www.asics.ws ----
+---- ----
+---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
+---- ----
+---------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2000 Richard Herveille ----
+---- richard@asics.ws ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+---- ----
+---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
+---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
+---- POSSIBILITY OF SUCH DAMAGE. ----
+---- ----
+---------------------------------------------------------------------
+
+-- CVS Log
+--
+-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
+--
+-- $Date: 2009-01-20 10:38:45 $
+-- $Revision: 1.8 $
+-- $Author: rherveille $
+-- $Locker: $
+-- $State: Exp $
+--
+-- Change History:
+-- Revision 1.7 2004/03/14 10:17:03 rherveille
+-- Fixed simulation issue when writing to CR register
+--
+-- Revision 1.6 2003/08/09 07:01:13 rherveille
+-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+-- Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+-- Revision 1.5 2003/02/01 02:03:06 rherveille
+-- Fixed a few 'arbitration lost' bugs. VHDL version only.
+--
+-- Revision 1.4 2002/12/26 16:05:47 rherveille
+-- Core is now a Multimaster I2C controller.
+--
+-- Revision 1.3 2002/11/30 22:24:37 rherveille
+-- Cleaned up code
+--
+-- Revision 1.2 2001/11/10 10:52:44 rherveille
+-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+entity i2c_master_top is
+ generic(
+ ARST_LVL : std_logic := '0' -- asynchronous reset level
+ );
+ port (
+ -- wishbone signals
+ wb_clk_i : in std_logic; -- master clock input
+ wb_rst_i : in std_logic := '0'; -- synchronous active high reset
+ arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
+ wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
+ wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
+ wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
+ wb_we_i : in std_logic; -- Write enable input
+ wb_stb_i : in std_logic; -- Strobe signals / core select signal
+ wb_cyc_i : in std_logic; -- Valid bus cycle input
+ wb_ack_o : out std_logic; -- Bus cycle acknowledge output
+ wb_inta_o : out std_logic; -- interrupt request output signal
+
+ -- i2c lines
+ scl_pad_i : in std_logic; -- i2c clock line input
+ scl_pad_o : out std_logic; -- i2c clock line output
+ scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
+ sda_pad_i : in std_logic; -- i2c data line input
+ sda_pad_o : out std_logic; -- i2c data line output
+ sda_padoen_o : out std_logic -- i2c data line output enable, active low
+ );
+end entity i2c_master_top;
+
+architecture structural of i2c_master_top is
+ component i2c_master_byte_ctrl is
+ port (
+ clk : in std_logic;
+ rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
+ nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
+ ena : in std_logic; -- core enable signal
+
+ clk_cnt : in unsigned(15 downto 0); -- 4x SCL
+
+ -- input signals
+ start,
+ stop,
+ read,
+ write,
+ ack_in : std_logic;
+ din : in std_logic_vector(7 downto 0);
+
+ -- output signals
+ cmd_ack : out std_logic;
+ ack_out : out std_logic;
+ i2c_busy : out std_logic;
+ i2c_al : out std_logic;
+ dout : out std_logic_vector(7 downto 0);
+
+ -- i2c lines
+ scl_i : in std_logic; -- i2c clock line input
+ scl_o : out std_logic; -- i2c clock line output
+ scl_oen : out std_logic; -- i2c clock line output enable, active low
+ sda_i : in std_logic; -- i2c data line input
+ sda_o : out std_logic; -- i2c data line output
+ sda_oen : out std_logic -- i2c data line output enable, active low
+ );
+ end component i2c_master_byte_ctrl;
+
+ -- registers
+ signal prer : unsigned(15 downto 0); -- clock prescale register
+ signal ctr : std_logic_vector(7 downto 0); -- control register
+ signal txr : std_logic_vector(7 downto 0); -- transmit register
+ signal rxr : std_logic_vector(7 downto 0); -- receive register
+ signal cr : std_logic_vector(7 downto 0); -- command register
+ signal sr : std_logic_vector(7 downto 0); -- status register
+
+ -- internal reset signal
+ signal rst_i : std_logic;
+
+ -- wishbone write access
+ signal wb_wacc : std_logic;
+
+ -- internal acknowledge signal
+ signal iack_o : std_logic;
+
+ -- done signal: command completed, clear command register
+ signal done : std_logic;
+
+ -- command register signals
+ signal sta, sto, rd, wr, ack, iack : std_logic;
+
+ signal core_en : std_logic; -- core enable signal
+ signal ien : std_logic; -- interrupt enable signal
+
+ -- status register signals
+ signal irxack, rxack : std_logic; -- received aknowledge from slave
+ signal tip : std_logic; -- transfer in progress
+ signal irq_flag : std_logic; -- interrupt pending flag
+ signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
+ signal i2c_al, al : std_logic; -- arbitration lost
+
+begin
+ -- generate internal reset signal
+ rst_i <= arst_i xor ARST_LVL;
+
+ -- generate acknowledge output signal
+ gen_ack_o : process(wb_clk_i)
+ begin
+ if (wb_clk_i'event and wb_clk_i = '1') then
+ iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
+ end if;
+ end process gen_ack_o;
+ wb_ack_o <= iack_o;
+
+ -- generate wishbone write access signal
+ wb_wacc <= wb_we_i and iack_o;
+
+ -- assign wb_dat_o
+ assign_dato : process(wb_clk_i)
+ begin
+ if (wb_clk_i'event and wb_clk_i = '1') then
+ case wb_adr_i is
+ when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
+ when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
+ when "010" => wb_dat_o <= ctr;
+ when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
+ when "100" => wb_dat_o <= sr; -- write is command register CR
+
+ -- Debugging registers:
+ -- These registers are not documented.
+ -- Functionality could change in future releases
+ when "101" => wb_dat_o <= txr;
+ when "110" => wb_dat_o <= cr;
+ when "111" => wb_dat_o <= (others => '0');
+ when others => wb_dat_o <= (others => 'X'); -- for simulation only
+ end case;
+ end if;
+ end process assign_dato;
+
+
+ -- generate registers (CR, SR see below)
+ gen_regs: process(rst_i, wb_clk_i)
+ begin
+ if (rst_i = '0') then
+ prer <= (others => '1');
+ ctr <= (others => '0');
+ txr <= (others => '0');
+ elsif (wb_clk_i'event and wb_clk_i = '1') then
+ if (wb_rst_i = '1') then
+ prer <= (others => '1');
+ ctr <= (others => '0');
+ txr <= (others => '0');
+ elsif (wb_wacc = '1') then
+ case wb_adr_i is
+ when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
+ when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
+ when "010" => ctr <= wb_dat_i;
+ when "011" => txr <= wb_dat_i;
+ when "100" => null; --write to CR, avoid executing the others clause
+
+ -- illegal cases, for simulation only
+ when others =>
+ report ("Illegal write address, setting all registers to unknown.");
+ prer <= (others => 'X');
+ ctr <= (others => 'X');
+ txr <= (others => 'X');
+ end case;
+ end if;
+ end if;
+ end process gen_regs;
+
+
+ -- generate command register
+ gen_cr: process(rst_i, wb_clk_i)
+ begin
+ if (rst_i = '0') then
+ cr <= (others => '0');
+ elsif (wb_clk_i'event and wb_clk_i = '1') then
+ if (wb_rst_i = '1') then
+ cr <= (others => '0');
+ elsif (wb_wacc = '1') then
+ if ( (core_en = '1') and (wb_adr_i = "100") ) then
+ -- only take new commands when i2c core enabled
+ -- pending commands are finished
+ cr <= wb_dat_i;
+ end if;
+ else
+ if (done = '1' or i2c_al = '1') then
+ cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
+ end if;
+
+ cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
+ cr(0) <= '0'; -- clear IRQ_ACK bit
+ end if;
+ end if;
+ end process gen_cr;
+
+ -- decode command register
+ sta <= cr(7);
+ sto <= cr(6);
+ rd <= cr(5);
+ wr <= cr(4);
+ ack <= cr(3);
+ iack <= cr(0);
+
+ -- decode control register
+ core_en <= ctr(7);
+ ien <= ctr(6);
+
+ -- hookup byte controller block
+ byte_ctrl: i2c_master_byte_ctrl
+ port map (
+ clk => wb_clk_i,
+ rst => wb_rst_i,
+ nReset => rst_i,
+ ena => core_en,
+ clk_cnt => prer,
+ start => sta,
+ stop => sto,
+ read => rd,
+ write => wr,
+ ack_in => ack,
+ i2c_busy => i2c_busy,
+ i2c_al => i2c_al,
+ din => txr,
+ cmd_ack => done,
+ ack_out => irxack,
+ dout => rxr,
+ scl_i => scl_pad_i,
+ scl_o => scl_pad_o,
+ scl_oen => scl_padoen_o,
+ sda_i => sda_pad_i,
+ sda_o => sda_pad_o,
+ sda_oen => sda_padoen_o
+ );
+
+
+ -- status register block + interrupt request signal
+ st_irq_block : block
+ begin
+ -- generate status register bits
+ gen_sr_bits: process (wb_clk_i, rst_i)
+ begin
+ if (rst_i = '0') then
+ al <= '0';
+ rxack <= '0';
+ tip <= '0';
+ irq_flag <= '0';
+ elsif (wb_clk_i'event and wb_clk_i = '1') then
+ if (wb_rst_i = '1') then
+ al <= '0';
+ rxack <= '0';
+ tip <= '0';
+ irq_flag <= '0';
+ else
+ al <= i2c_al or (al and not sta);
+ rxack <= irxack;
+ tip <= (rd or wr);
+
+ -- interrupt request flag is always generated
+ irq_flag <= (done or i2c_al or irq_flag) and not iack;
+ end if;
+ end if;
+ end process gen_sr_bits;
+
+ -- generate interrupt request signals
+ gen_irq: process (wb_clk_i, rst_i)
+ begin
+ if (rst_i = '0') then
+ wb_inta_o <= '0';
+ elsif (wb_clk_i'event and wb_clk_i = '1') then
+ if (wb_rst_i = '1') then
+ wb_inta_o <= '0';
+ else
+ -- interrupt signal is only generated when IEN (interrupt enable bit) is set
+ wb_inta_o <= irq_flag and ien;
+ end if;
+ end if;
+ end process gen_irq;
+
+ -- assign status register bits
+ sr(7) <= rxack;
+ sr(6) <= i2c_busy;
+ sr(5) <= al;
+ sr(4 downto 2) <= (others => '0'); -- reserved
+ sr(1) <= tip;
+ sr(0) <= irq_flag;
+ end block;
+
+end architecture structural;
diff --git a/modules/wishbone/wb_onewire_master/sockit_owm.v b/modules/wishbone/wb_onewire_master/sockit_owm.v
new file mode 100644
index 0000000000000000000000000000000000000000..b4dd74e8eb1aa2dd984f4ecdf00266a863f0a76a
--- /dev/null
+++ b/modules/wishbone/wb_onewire_master/sockit_owm.v
@@ -0,0 +1,419 @@
+//////////////////////////////////////////////////////////////////////////////
+// //
+// Minimalistic 1-wire (onewire) master with Avalon MM bus interface //
+// //
+// Copyright (C) 2010 Iztok Jeras //
+// //
+//////////////////////////////////////////////////////////////////////////////
+// //
+// This RTL is free hardware: you can redistribute it and/or modify //
+// it under the terms of the GNU Lesser General Public License //
+// as published by the Free Software Foundation, either //
+// version 3 of the License, or (at your option) any later version. //
+// //
+// This RTL is distributed in the hope that it will be useful, //
+// but WITHOUT ANY WARRANTY; without even the implied warranty of //
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
+// GNU General Public License for more details. //
+// //
+// You should have received a copy of the GNU General Public License //
+// along with this program. If not, see <http://www.gnu.org/licenses/>. //
+// //
+//////////////////////////////////////////////////////////////////////////////
+
+
+//////////////////////////////////////////////////////////////////////////////
+// //
+// The clock divider parameter is computed with the next formula: //
+// //
+// CDR_N = f_CLK * BTP_N - 1 (example: CDR_N = 1MHz * 5.0us - 1 = 5-1) //
+// CDR_O = f_CLK * BTP_O - 1 (example: CDR_O = 1MHz * 1.0us - 1 = 1-1) //
+// //
+// If the dividing factor is not a round integer, than the timing of the //
+// controller will be slightly off, and would support only a subset of //
+// 1-wire devices with timing closer to the typical 30us slot. //
+// //
+// Base time periods BTP_N = "5.0" and BTP_O = "1.0" are optimized for //
+// onewire timing. The default timing restricts the range of available //
+// frequences to multiples of 1MHz. //
+// //
+// If even this restrictions are too strict use timing BTP_N = "6.0" and //
+// BTP_O = "0.5", where the actual periods can be in the range: //
+// 6.0us <= BTP_N <= 7.5us //
+// 0.5us <= BTP_O <= 0.66us //
+// //
+// A third timing option is available for normal mode BTP_N = "7.5", this //
+// option is optimized for logic size. //
+// //
+//////////////////////////////////////////////////////////////////////////////
+
+module sockit_owm #(
+ // enable implementation of optional functionality
+ parameter OVD_E = 1, // overdrive functionality is implemented by default
+ parameter CDR_E = 1, // clock divider register is implemented by default
+ // interface parameters
+ parameter BDW = 32, // bus data width
+ parameter OWN = 1, // number of 1-wire ports
+ // computed bus address port width
+`ifdef __ICARUS__
+ parameter BAW = (BDW==32) ? 1 : 2,
+`else
+ parameter BAW = 1, // TODO, the above is correct, but does not work well with Altera SOPC Builder
+`endif
+ // base time period
+ parameter BTP_N = "5.0", // normal mode (5.0us, options are "7.5", "5.0" and "6.0")
+ parameter BTP_O = "1.0", // overdrive mode (1.0us, options are "1.0", and "0.5")
+ // normal mode timing
+ parameter T_RSTH_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset high
+ parameter T_RSTL_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset low
+ parameter T_RSTP_N = (BTP_N == "7.5") ? 10 : (BTP_N == "5.0") ? 15 : 10, // reset presence pulse
+ parameter T_DAT0_N = (BTP_N == "7.5") ? 8 : (BTP_N == "5.0") ? 12 : 10, // bit 0 low
+ parameter T_DAT1_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // bit 1 low
+ parameter T_BITS_N = (BTP_N == "7.5") ? 2 : (BTP_N == "5.0") ? 3 : 2, // bit sample
+ parameter T_RCVR_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // recovery
+ parameter T_IDLE_N = (BTP_N == "7.5") ? 128 : (BTP_N == "5.0") ? 200 : 160, // idle timer
+ // overdrive mode timing
+ parameter T_RSTH_O = (BTP_O == "1.0") ? 48 : 96, // reset high
+ parameter T_RSTL_O = (BTP_O == "1.0") ? 48 : 96, // reset low
+ parameter T_RSTP_O = (BTP_O == "1.0") ? 10 : 15, // reset presence pulse
+ parameter T_DAT0_O = (BTP_O == "1.0") ? 6 : 12, // bit 0 low
+ parameter T_DAT1_O = (BTP_O == "1.0") ? 1 : 2, // bit 1 low
+ parameter T_BITS_O = (BTP_O == "1.0") ? 2 : 3, // bit sample
+ parameter T_RCVR_O = (BTP_O == "1.0") ? 2 : 4, // recovery
+ parameter T_IDLE_O = (BTP_O == "1.0") ? 96 : 192, // idle timer
+ // clock divider ratios (defaults are for a 2MHz clock)
+ parameter CDR_N = 5-1, // normal mode
+ parameter CDR_O = 1-1 // overdrive mode
+)(
+ // system signals
+ input clk,
+ input rst,
+ // CPU bus interface
+ input bus_ren, // read enable
+ input bus_wen, // write enable
+ input [BAW-1:0] bus_adr, // address
+ input [BDW-1:0] bus_wdt, // write data
+ output [BDW-1:0] bus_rdt, // read data
+ output bus_irq, // interrupt request
+ // 1-wire interface
+ output [OWN-1:0] owr_p, // output power enable
+ output [OWN-1:0] owr_e, // output pull down enable
+ input [OWN-1:0] owr_i // input from bidirectional wire
+);
+
+//////////////////////////////////////////////////////////////////////////////
+// local parameters
+//////////////////////////////////////////////////////////////////////////////
+
+// size of combined power and select registers
+localparam PDW = (BDW==32) ? 24 : 8;
+
+// size of boudrate generator counter (divider for normal mode is largest)
+localparam CDW = CDR_E ? ((BDW==32) ? 16 : 8) : $clog2(CDR_N);
+
+// size of port select signal
+localparam SDW = $clog2(OWN);
+
+// size of cycle timing counter
+localparam TDW = (T_RSTH_O+T_RSTL_O) > (T_RSTH_N+T_RSTL_N)
+ ? $clog2(T_RSTH_O+T_RSTL_O) : $clog2(T_RSTH_N+T_RSTL_N);
+
+//////////////////////////////////////////////////////////////////////////////
+// local signals
+//////////////////////////////////////////////////////////////////////////////
+
+// address dependent write enable
+wire bus_ren_ctl_sts;
+wire bus_wen_ctl_sts;
+wire bus_wen_pwr_sel;
+wire bus_wen_cdr_n;
+wire bus_wen_cdr_o;
+
+// read data bus segments
+wire [7:0] bus_rdt_ctl_sts;
+wire [PDW-1:0] bus_rdt_pwr_sel;
+
+// clock divider
+reg [CDW-1:0] div;
+reg [CDW-1:0] cdr_n;
+reg [CDW-1:0] cdr_o;
+wire pls;
+
+// cycle control and status
+reg owr_cyc; // cycle status
+reg [TDW-1:0] cnt; // cycle counter
+
+// port select
+//generate if (OWN>1) begin : sel_declaration
+reg [SDW-1:0] owr_sel;
+//end endgenerate
+
+// modified input data for overdrive
+wire req_ovd;
+
+// onewire signals
+reg [OWN-1:0] owr_pwr; // power
+reg owr_ovd; // overdrive
+reg owr_rst; // reset
+reg owr_dat; // data bit
+reg owr_smp; // sample bit
+
+reg owr_oen; // output enable
+wire owr_iln; // input line
+
+// interrupt signals
+reg irq_ena; // interrupt enable
+reg irq_sts; // interrupt status
+
+// timing signals
+wire [TDW-1:0] t_idl ; // idle cycle time
+wire [TDW-1:0] t_rst ; // reset cycle time
+wire [TDW-1:0] t_bit ; // data bit cycle time
+wire [TDW-1:0] t_rstp; // reset presence pulse sampling time
+wire [TDW-1:0] t_rsth; // reset release time
+wire [TDW-1:0] t_dat0; // data bit 0 release time
+wire [TDW-1:0] t_dat1; // data bit 1 release time
+wire [TDW-1:0] t_bits; // data bit sampling time
+wire [TDW-1:0] t_zero; // end of cycle time
+
+//////////////////////////////////////////////////////////////////////////////
+// cycle timing
+//////////////////////////////////////////////////////////////////////////////
+
+// idle time
+assign t_idl = req_ovd ? T_IDLE_O : T_IDLE_N ;
+// reset cycle time (reset low + reset hight)
+assign t_rst = req_ovd ? T_RSTL_O + T_RSTH_O : T_RSTL_N + T_RSTH_N ;
+// data bit cycle time (write 0 + recovery)
+assign t_bit = req_ovd ? T_DAT0_O + + T_RCVR_O : T_DAT0_N + T_RCVR_N;
+
+// reset presence pulse sampling time (reset high - reset presence)
+assign t_rstp = owr_ovd ? T_RSTH_O - T_RSTP_O : T_RSTH_N - T_RSTP_N ;
+// reset release time (reset high)
+assign t_rsth = owr_ovd ? T_RSTH_O : T_RSTH_N ;
+
+// data bit 0 release time (write bit 0 - write bit 0 + recovery)
+assign t_dat0 = owr_ovd ? T_DAT0_O - T_DAT0_O + T_RCVR_O : T_DAT0_N - T_DAT0_N + T_RCVR_N;
+// data bit 1 release time (write bit 0 - write bit 1 + recovery)
+assign t_dat1 = owr_ovd ? T_DAT0_O - T_DAT1_O + T_RCVR_O : T_DAT0_N - T_DAT1_N + T_RCVR_N;
+// data bit sampling time (write bit 0 - write bit 1 + recovery)
+assign t_bits = owr_ovd ? T_DAT0_O - T_BITS_O + T_RCVR_O : T_DAT0_N - T_BITS_N + T_RCVR_N;
+
+// end of cycle time
+assign t_zero = 'd0;
+
+//////////////////////////////////////////////////////////////////////////////
+// bus read
+//////////////////////////////////////////////////////////////////////////////
+
+// bus segnemt - controll/status register
+assign bus_rdt_ctl_sts = {irq_ena, irq_sts, 1'b0, owr_pwr[0], owr_cyc, owr_ovd, owr_rst, owr_dat};
+
+// bus segnemt - power and select register
+generate
+ if (BDW==32) begin
+ if (OWN>1) begin
+ assign bus_rdt_pwr_sel = {{16-OWN{1'b0}}, owr_pwr, 4'h0, {4-SDW{1'b0}}, owr_sel};
+ end else begin
+ assign bus_rdt_pwr_sel = 24'h0000_00;
+ end
+ end else if (BDW==8) begin
+ if (OWN>1) begin
+ assign bus_rdt_pwr_sel = {{ 4-OWN{1'b0}}, owr_pwr, {4-SDW{1'b0}}, owr_sel};
+ end else begin
+ assign bus_rdt_pwr_sel = 8'hxx;
+ end
+ end
+endgenerate
+
+// bus read data
+generate if (BDW==32) begin
+ assign bus_rdt = (bus_adr[0]==1'b0) ? {bus_rdt_pwr_sel, bus_rdt_ctl_sts} : (cdr_o << 16 | cdr_n);
+end else if (BDW==8) begin
+ assign bus_rdt = (bus_adr[1]==1'b0) ? ((bus_adr[0]==1'b0) ? bus_rdt_ctl_sts
+ : bus_rdt_pwr_sel)
+ : ((bus_adr[0]==1'b0) ? cdr_n
+ : cdr_o );
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// bus write
+//////////////////////////////////////////////////////////////////////////////
+
+// combined write/read enable and address decoder
+generate if (BDW==32) begin
+ assign bus_ren_ctl_sts = bus_ren & bus_adr[0] == 1'b0;
+ assign bus_wen_ctl_sts = bus_wen & bus_adr[0] == 1'b0;
+ assign bus_wen_pwr_sel = bus_wen & bus_adr[0] == 1'b0;
+ assign bus_wen_cdr_n = bus_wen & bus_adr[0] == 1'b1;
+ assign bus_wen_cdr_o = bus_wen & bus_adr[0] == 1'b1;
+end else if (BDW==8) begin
+ assign bus_ren_ctl_sts = bus_ren & bus_adr[1:0] == 2'b00;
+ assign bus_wen_ctl_sts = bus_wen & bus_adr[1:0] == 2'b00;
+ assign bus_wen_pwr_sel = bus_wen & bus_adr[1:0] == 2'b01;
+ assign bus_wen_cdr_n = bus_wen & bus_adr[1:0] == 2'b10;
+ assign bus_wen_cdr_o = bus_wen & bus_adr[1:0] == 2'b11;
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// clock divider
+//////////////////////////////////////////////////////////////////////////////
+
+// clock divider ratio registers
+generate
+ if (CDR_E) begin
+ if (BDW==32) begin
+ always @ (posedge clk, posedge rst)
+ if (rst) begin
+ cdr_n <= CDR_N;
+ cdr_o <= CDR_O;
+ end else begin
+ if (bus_wen_cdr_n) cdr_n <= bus_wdt[15: 0];
+ if (bus_wen_cdr_o) cdr_o <= bus_wdt[31:16];
+ end
+ end else if (BDW==8) begin
+ always @ (posedge clk, posedge rst)
+ if (rst) begin
+ cdr_n <= CDR_N;
+ cdr_o <= CDR_O;
+ end else begin
+ if (bus_wen_cdr_n) cdr_n <= bus_wdt;
+ if (bus_wen_cdr_o) cdr_o <= bus_wdt;
+ end
+ end
+ end else begin
+ initial begin
+ cdr_n = CDR_N;
+ cdr_o = CDR_O;
+ end
+ end
+endgenerate
+
+// clock divider
+always @ (posedge clk, posedge rst)
+if (rst) div <= 'd0;
+else begin
+ if (bus_wen) div <= 'd0;
+ else div <= pls ? 'd0 : div + owr_cyc;
+end
+
+// divided clock pulse
+assign pls = (div == (owr_ovd ? cdr_o : cdr_n));
+
+//////////////////////////////////////////////////////////////////////////////
+// power and select register
+//////////////////////////////////////////////////////////////////////////////
+
+// select and power register implementation
+generate if (OWN>1) begin : sel_implementation
+ // port select
+ always @ (posedge clk, posedge rst)
+ if (rst) owr_sel <= {SDW{1'b0}};
+ else if (bus_wen_pwr_sel) owr_sel <= bus_wdt[(BDW==32 ? 8 : 0)+:SDW];
+
+ // power delivery
+ always @ (posedge clk, posedge rst)
+ if (rst) owr_pwr <= {OWN{1'b0}};
+ else if (bus_wen_pwr_sel) owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN];
+end else begin
+ // port select
+ initial owr_sel <= 'd0;
+ // power delivery
+ always @ (posedge clk, posedge rst)
+ if (rst) owr_pwr <= 1'b0;
+ else if (bus_wen_ctl_sts) owr_pwr <= bus_wdt[4];
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////////
+// interrupt logic
+//////////////////////////////////////////////////////////////////////////////
+
+// bus interrupt
+assign bus_irq = irq_ena & irq_sts;
+
+// interrupt enable
+always @ (posedge clk, posedge rst)
+if (rst) irq_ena <= 1'b0;
+else if (bus_wen_ctl_sts) irq_ena <= bus_wdt[7];
+
+// transmit status (active after onewire cycle ends)
+always @ (posedge clk, posedge rst)
+if (rst) irq_sts <= 1'b0;
+else begin
+ if (bus_wen_ctl_sts) irq_sts <= 1'b0;
+ else if (pls & (cnt == t_zero)) irq_sts <= 1'b1;
+ else if (bus_ren_ctl_sts) irq_sts <= 1'b0;
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// onewire state machine
+//////////////////////////////////////////////////////////////////////////////
+
+assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0;
+
+// overdrive
+always @ (posedge clk, posedge rst)
+if (rst) owr_ovd <= 1'b0;
+else if (bus_wen_ctl_sts) owr_ovd <= req_ovd;
+
+// reset
+always @ (posedge clk, posedge rst)
+if (rst) owr_rst <= 1'b0;
+else if (bus_wen_ctl_sts) owr_rst <= bus_wdt[1];
+
+// transmit data, reset, overdrive
+always @ (posedge clk, posedge rst)
+if (rst) owr_dat <= 1'b0;
+else begin
+ if (bus_wen_ctl_sts) owr_dat <= bus_wdt[0];
+ else if (pls & (cnt == t_zero)) owr_dat <= owr_smp;
+end
+
+// onewire cycle status
+always @ (posedge clk, posedge rst)
+if (rst) owr_cyc <= 1'b0;
+else begin
+ if (bus_wen_ctl_sts) owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0];
+ else if (pls & (cnt == t_zero)) owr_cyc <= 1'b0;
+end
+
+// state counter (initial value depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst) cnt <= 0;
+else begin
+ if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1;
+ else if (pls) cnt <= cnt - 'd1;
+end
+
+// receive data (sampling point depends whether the cycle is reset or data)
+always @ (posedge clk)
+if (pls) begin
+ if ( owr_rst & (cnt == t_rstp)) owr_smp <= owr_iln; // presence detect
+ else if (~owr_rst & (cnt == t_bits)) owr_smp <= owr_iln; // read data bit
+end
+
+// output register (switch point depends whether the cycle is reset or data)
+always @ (posedge clk, posedge rst)
+if (rst) owr_oen <= 1'b0;
+else begin
+ if (bus_wen_ctl_sts) owr_oen <= ~&bus_wdt[1:0];
+ else if (pls) begin
+ if (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0; // reset
+ else if (owr_dat & (cnt == t_dat1)) owr_oen <= 1'b0; // write 1, read
+ else if ( (cnt == t_dat0)) owr_oen <= 1'b0; // write 0
+ end
+end
+
+//////////////////////////////////////////////////////////////////////////////
+// IO
+//////////////////////////////////////////////////////////////////////////////
+
+// only one 1-wire line cn be accessed at the same time
+assign owr_e = owr_oen << owr_sel;
+// all 1-wire lines can be powered independently
+assign owr_p = owr_pwr;
+
+// 1-wire line status read multiplexer
+assign owr_iln = owr_i [owr_sel];
+
+endmodule
diff --git a/modules/wishbone/wb_onewire_master/sockit_owr.pdf b/modules/wishbone/wb_onewire_master/sockit_owr.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..f9e5f97d10767a5dbf2850a4ad685f8b0d3bdc58
Binary files /dev/null and b/modules/wishbone/wb_onewire_master/sockit_owr.pdf differ
diff --git a/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0f65402a3f4c7402df2d3655e43dcf6b9bed2dca
--- /dev/null
+++ b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
@@ -0,0 +1,43 @@
+module wishbone2bus #(
+ parameter AW = 2, // address width
+ parameter DW = 32, // data width
+ parameter SW = DW/8 // select width
+)(
+ // Wishbone master port
+ input wire wb_cyc, // cycle
+ input wire wb_stb, // strobe
+ input wire wb_we, // write enable
+ input wire [AW-1:0] wb_adr, // address
+ input wire [SW-1:0] wb_sel, // byte select
+ input wire [DW-1:0] wb_dat_w, // write data
+ output wire [DW-1:0] wb_dat_r, // read data
+ output wire wb_ack, // acknowledge
+ output wire wb_err, // error
+ output wire wb_rty, // retry
+ // Avalon slave port
+ output wire bus_wen, // write enable
+ output wire bus_ren, // read enable
+ output wire [AW-1:0] bus_adr, // address
+ output wire [DW-1:0] bus_wdt, // write data
+ input wire [DW-1:0] bus_rdt // read data
+);
+
+// bus write and read enable
+assign bus_wen = wb_cyc & wb_stb & wb_we;
+assign bus_ren = wb_cyc & wb_stb & ~wb_we;
+
+// address
+assign bus_adr = wb_adr;
+
+// write data
+assign bus_wdt = wb_dat_w;
+
+// read data
+assign wb_dat_r = bus_rdt;
+
+// error if not full width access else acknowledge
+assign wb_ack = &wb_sel;
+assign wb_err = ~&wb_sel;
+assign wb_rty = 1'b0;
+
+endmodule
diff --git a/modules/wishbone/wb_simple_timer/wb_tics.vhd b/modules/wishbone/wb_simple_timer/wb_tics.vhd
index d7acc1388bf909332507783fb592066676f51731..c60c1043c3696e76b35ada5cbb2ac6d3c82a1b66 100644
--- a/modules/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/wb_tics.vhd
@@ -27,7 +27,6 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-use work.common_components.all;
entity wb_tics is