softpll: sync up register definitions with the multichannel SPLL HDL

softpll/hw/softpll_regs.h

@@ -3,7 +3,7 @@
 
   * File           : softpll_regs.h
   * Author         : auto-generated by wbgen2 from spll_wb_slave.wb
-  * Created        : Wed Mar 20 14:50:14 2013
+  * Created        : Thu Jul 25 11:14:53 2013
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
@@ -33,20 +33,26 @@
 
 /* definitions for register: SPLL Control/Status Register */
 
+/* definitions for field: Unused (kept for software compatibility). in reg: SPLL Control/Status Register */
+#define SPLL_CSR_UNUSED0_MASK                 WBGEN2_GEN_MASK(0, 6)
+#define SPLL_CSR_UNUSED0_SHIFT                0
+#define SPLL_CSR_UNUSED0_W(value)             WBGEN2_GEN_WRITE(value, 0, 6)
+#define SPLL_CSR_UNUSED0_R(reg)               WBGEN2_GEN_READ(reg, 0, 6)
+
 /* definitions for field: Number of reference channels (max: 32) in reg: SPLL Control/Status Register */
-#define SPLL_CSR_N_REF_MASK                   WBGEN2_GEN_MASK(0, 6)
-#define SPLL_CSR_N_REF_SHIFT                  0
-#define SPLL_CSR_N_REF_W(value)               WBGEN2_GEN_WRITE(value, 0, 6)
-#define SPLL_CSR_N_REF_R(reg)                 WBGEN2_GEN_READ(reg, 0, 6)
+#define SPLL_CSR_N_REF_MASK                   WBGEN2_GEN_MASK(8, 6)
+#define SPLL_CSR_N_REF_SHIFT                  8
+#define SPLL_CSR_N_REF_W(value)               WBGEN2_GEN_WRITE(value, 8, 6)
+#define SPLL_CSR_N_REF_R(reg)                 WBGEN2_GEN_READ(reg, 8, 6)
 
 /* definitions for field: Number of output channels (max: 8) in reg: SPLL Control/Status Register */
-#define SPLL_CSR_N_OUT_MASK                   WBGEN2_GEN_MASK(8, 3)
-#define SPLL_CSR_N_OUT_SHIFT                  8
-#define SPLL_CSR_N_OUT_W(value)               WBGEN2_GEN_WRITE(value, 8, 3)
-#define SPLL_CSR_N_OUT_R(reg)                 WBGEN2_GEN_READ(reg, 8, 3)
+#define SPLL_CSR_N_OUT_MASK                   WBGEN2_GEN_MASK(16, 3)
+#define SPLL_CSR_N_OUT_SHIFT                  16
+#define SPLL_CSR_N_OUT_W(value)               WBGEN2_GEN_WRITE(value, 16, 3)
+#define SPLL_CSR_N_OUT_R(reg)                 WBGEN2_GEN_READ(reg, 16, 3)
 
 /* definitions for field: Debug queue supported in reg: SPLL Control/Status Register */
-#define SPLL_CSR_DBG_SUPPORTED                WBGEN2_GEN_MASK(11, 1)
+#define SPLL_CSR_DBG_SUPPORTED                WBGEN2_GEN_MASK(19, 1)
 
 /* definitions for register: External Clock Control Register */
 
@@ -228,28 +234,32 @@ PACKED struct SPLL_WB {
   uint32_t CSR;
   /* [0x4]: REG External Clock Control Register */
   uint32_t ECCR;
-  /* [0x8]: REG Output Channel Control Register */
+  /* padding to: 4 words */
+  uint32_t __padding_0[2];
+  /* [0x10]: REG Output Channel Control Register */
   uint32_t OCCR;
-  /* [0xc]: REG Reference Channel Tagging Enable Register */
+  /* [0x14]: REG Reference Channel Tagging Enable Register */
   uint32_t RCER;
-  /* [0x10]: REG Output Channel Tagging Enable Register */
+  /* [0x18]: REG Output Channel Tagging Enable Register */
   uint32_t OCER;
-  /* [0x14]: REG Helper DAC Output */
+  /* padding to: 8 words */
+  uint32_t __padding_1[1];
+  /* [0x20]: REG Helper DAC Output */
   uint32_t DAC_HPLL;
-  /* [0x18]: REG Main DAC Output */
+  /* [0x24]: REG Main DAC Output */
   uint32_t DAC_MAIN;
-  /* [0x1c]: REG DDMTD Deglitcher threshold */
+  /* [0x28]: REG DDMTD Deglitcher threshold */
   uint32_t DEGLITCH_THR;
-  /* [0x20]: REG Debug FIFO Register - SPLL side */
+  /* [0x2c]: REG Debug FIFO Register - SPLL side */
   uint32_t DFR_SPLL;
-  /* [0x24]: REG Counter Resync Register - input channels */
+  /* [0x30]: REG Counter Resync Register - input channels */
   uint32_t CRR_IN;
-  /* [0x28]: REG Counter Resync Register - output channels */
+  /* [0x34]: REG Counter Resync Register - output channels */
   uint32_t CRR_OUT;
-  /* [0x2c]: REG Aux clock configuration register */
+  /* [0x38]: REG Aux clock configuration register */
   uint32_t AUX_CR;
   /* padding to: 16 words */
-  uint32_t __padding_0[4];
+  uint32_t __padding_2[1];
   /* [0x40]: REG Interrupt disable register */
   uint32_t EIC_IDR;
   /* [0x44]: REG Interrupt enable register */