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This is an archived project. Repository and other project resources are read-only.
hdl-core-lib
wr-cores
wrpc-sw
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greg_tmp_mess
821e1271
·
greg_tmp_mess: adding lm32 linker section and the end of ram and handling code...
·
12 years ago
505
3
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timing-starter-kit
d90b5ca5
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Use a work-around hack
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12 years ago
484
2
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tom-strip-delays-verilog-sim
47ea44fe
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Stripped-down version which initializes the network/timing stuff without...
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12 years ago
453
2
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tom-trigger-dist-demo
23e580cd
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tools: crude etherbone LM32 loader.
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12 years ago
408
2
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tom-bangbang-pd
0c3db9e7
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compilation fixes
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12 years ago
396
4
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