hdlmake simulation test

tb/lbc/Manifest.py

+action = "simulation"
+target = "ghdl"
+
+files = "tb_lbc.vhd"
+

tb/lbc/tb_lbc.vhd

+-------------------------------------------------------------------------------
+-- TDC Core / CERN
+-------------------------------------------------------------------------------
+--
+-- unit name: tb_lbc
+--
+-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
+--
+-- description: Test bench for leading bit counter
+--
+-- references: http://www.ohwr.org/projects/tdc-core
+--
+-------------------------------------------------------------------------------
+-- last changes:
+-- 2011-08-03 SB Created file
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_lbc is
+end entity;
+
+architecture tb of tb_lbc is
+begin
+    process begin
+        report "hello world";
+    end process;
+end architecture;