Remove default generic values

core/tdc_delayline.vhd

@@ -25,7 +25,7 @@ use UNISIM.vcomponents.all;
 
 entity tdc_delayline is
     generic (
-        g_WIDTH : positive := 4 -- number of CARRY4 elements
+        g_WIDTH : positive -- number of CARRY4 elements
     );
     port ( 
          clk_sample_i : in std_logic;

core/tdc_lbc.vhd

@@ -24,7 +24,7 @@ entity tdc_lbc is
     generic (
         -- Number of output bits.
         -- The number of input bits is 2^g_N-1.
-        g_N : positive := 4
+        g_N : positive
     );
     port (
          polarity_i   : in std_logic;