common.ucf

# ==== Clock input ====
NET "sys_clk" TNM_NET = CLK_125MHZ;
TIMESPEC TS_CLK_125MHZ = PERIOD CLK_125MHZ 8 ns;

# FPGA_CLK from CDCM61004, 125MHz
NET "clkin_p" LOC = G9 | IOSTANDARD = "LVDS_25";
NET "clkin_n" LOC = F10 | IOSTANDARD = "LVDS_25";

# AUX button 0
NET "resetin_n" LOC = C22 | IOSTANDARD = "LVCMOS18";

# ==== UART ====
NET "uart_rxd" LOC = A2 | IOSTANDARD = "LVCMOS25"; # FPGA input
NET "uart_txd" LOC = B2 | IOSTANDARD = "LVCMOS25"; # FPGA output

# ==== GPIO ====
NET "btn" LOC = D21 | IOSTANDARD = "LVCMOS18"; # AUX button 1
NET "led[0]" LOC = G19 | IOSTANDARD = "LVCMOS18"; # AUX LEDs
NET "led[1]" LOC = F20 | IOSTANDARD = "LVCMOS18";
NET "led[2]" LOC = F18 | IOSTANDARD = "LVCMOS18";
NET "led[3]" LOC = C20 | IOSTANDARD = "LVCMOS18";
NET "onewire" LOC = D4 | IOSTANDARD = "LVCMOS25";
NET "sdc" LOC = F7 | IOSTANDARD = "LVCMOS25";
NET "sda" LOC = F8 | IOSTANDARD = "LVCMOS25";

# ==== TDC ====
NET "test_clk_oe_n" LOC = V17 | IOSTANDARD = "LVCMOS25";
NET "test_clk_p" LOC = W17 | IOSTANDARD = "LVDS_25";
NET "test_clk_n" LOC = Y18 | IOSTANDARD = "LVDS_25";

NET "dummy" LOC = AA10 | IOSTANDARD = "LVCMOS25";

NET "tdc_signal_oe_n[0]" LOC = Y14 | IOSTANDARD = "LVCMOS25";
NET "tdc_signal_term_en[0]" LOC = AB5 | IOSTANDARD = "LVCMOS25";
NET "tdc_signal_p[0]" LOC = R11 | IOSTANDARD = "LVDS_25";
NET "tdc_signal_n[0]" LOC = T11 | IOSTANDARD = "LVDS_25";

NET "tdc_signal_oe_n[1]" LOC = W11 | IOSTANDARD = "LVCMOS25";
NET "tdc_signal_term_en[1]" LOC = AB6 | IOSTANDARD = "LVCMOS25";
NET "tdc_signal_p[1]" LOC = W12 | IOSTANDARD = "LVDS_25";
NET "tdc_signal_n[1]" LOC = Y12 | IOSTANDARD = "LVDS_25";

# ==== TDC core ====
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/inv_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/inv_signal" TIG;

INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/Mxor_inv_signal_xo<0>1" LOC = SLICE_X35Y0;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/Mxor_inv_signal_xo<0>1" LOC = SLICE_X35Y0;

INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/cmp_delayline/g_carry4[0].g_firstcarry4.cmp_CARRY4" LOC = SLICE_X30Y2;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/cmp_delayline/g_carry4[0].g_firstcarry4.cmp_CARRY4" LOC = SLICE_X32Y2;