demo: feedback through one IOB (optional)

demo/boards/spec/rtl/system.v

@@ -18,6 +18,8 @@
 
 `include "setup.v"
 
+`define USE_FMC_DIO
+
 module system(
 	input clkin_p,
 	input clkin_n,
@@ -41,7 +43,8 @@ module system(
 	output [1:0] tdc_signal_oe_n,
 	output [1:0] tdc_signal_term_en,
 	input [1:0] tdc_signal_p,
-	input [1:0] tdc_signal_n
+	input [1:0] tdc_signal_n,
+	inout dummy // unconnected FPGA pad
 );
 
 //------------------------------------------------------------------
@@ -533,14 +536,33 @@ assign tdc_signal_term_en[0] = 1'b1;
 IBUFDS ibuf_tdc_signal0(
 	.I(tdc_signal_p[0]),
 	.IB(tdc_signal_n[0]),
+`ifdef USE_FMC_DIO
 	.O(tdc_signal[0])
+`else
+	.O()
+`endif
 );
 assign tdc_signal_oe_n[1] = 1'b1;
 assign tdc_signal_term_en[1] = 1'b1;
 IBUFDS ibuf_tdc_signal1(
 	.I(tdc_signal_p[1]),
 	.IB(tdc_signal_n[1]),
+`ifdef USE_FMC_DIO
 	.O(tdc_signal[1])
+`else
+	.O()
+`endif
+);
+
+`ifndef USE_FMC_DIO
+wire test_clk_delayed;
+IOBUF d(
+	.T(1'b0),
+	.I(test_clk),
+	.O(test_clk_delayed),
+	.IO(dummy)
 );
+assign tdc_signal = {test_clk, test_clk_delayed};
+`endif
 
 endmodule

demo/boards/spec/synthesis/common.ucf

@@ -28,6 +28,8 @@ NET "test_clk_oe_n" LOC = V17 | IOSTANDARD = "LVCMOS25";
 NET "test_clk_p" LOC = W17 | IOSTANDARD = "LVDS_25";
 NET "test_clk_n" LOC = Y18 | IOSTANDARD = "LVDS_25";
 
+NET "dummy" LOC = AA10 | IOSTANDARD = "LVCMOS25";
+
 NET "tdc_signal_oe_n[0]" LOC = Y14 | IOSTANDARD = "LVCMOS25";
 NET "tdc_signal_term_en[0]" LOC = AB5 | IOSTANDARD = "LVCMOS25";
 NET "tdc_signal_p[0]" LOC = R11 | IOSTANDARD = "LVDS_25";