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PTS - Improve DDR memory test program
spec#39
· opened
Jun 27, 2012
by
Erik van der Bij
support
2
updated
Feb 12, 2019
V4 - DDR3 pending End-of-life
spec#38
· opened
Jul 10, 2012
by
Erik van der Bij
feature
1
updated
Feb 12, 2019
PTS - VHDL files are not stored in repository
spec#37
· opened
Jul 18, 2012
by
Erik van der Bij
support
0
updated
Feb 12, 2019
V4 - 3V3 regulator resistor values wrong
spec#36
· opened
Sep 21, 2012
by
Erik van der Bij
feature
0
updated
Feb 12, 2019
V4 - Add LED on FPGA DONE pin
spec#35
· opened
Nov 01, 2012
by
Projects
feature
0
updated
Feb 12, 2019
V4 - Plating of PCIe card edge connector not specified
spec#33
· opened
Dec 19, 2012
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
V4-0 - enlarge via size 450um to 550um
spec#32
· opened
Jan 11, 2013
by
Erik van der Bij
feature
0
updated
Feb 12, 2019
V4 - Consider adding connector to supply a fan
spec#31
· opened
Jun 19, 2013
by
Erik van der Bij
feature
0
updated
Feb 12, 2019
V4 - Space between miniUSB and JTAG connector must increase 1mm
spec#30
· opened
Oct 17, 2013
by
Benoit Rat
bug
0
updated
Feb 12, 2019
V4 - Reset timing of CDCM61004
spec#29
· opened
Feb 07, 2014
by
Tomasz Wlostowski
feature
0
updated
Feb 12, 2019
SPI flash PROM latency
spec#28
· opened
Mar 13, 2014
by
Magnus Sundal
0
updated
Feb 12, 2019
V4 - PCB revision resistors are set to 3 instead of 4.
spec#27
· opened
Mar 21, 2014
by
Projects
bug
1
updated
Feb 12, 2019
V4 - Manage T8 from P3V3_PCIE
spec#26
· opened
Mar 21, 2014
by
Projects
feature
0
updated
Feb 12, 2019
V4 - Automatic 1x PCIe
spec#25
· opened
Mar 21, 2014
by
Projects
feature
0
updated
Feb 12, 2019
V4 - Serial flash communication issue
spec#24
· opened
Mar 28, 2014
by
Projects
bug
0
updated
Feb 12, 2019
V4 - SFP cage type is obsolete, EOL
spec#1
· opened
Jan 25, 2018
by
Erik van der Bij
feature
0
updated
Feb 12, 2019
EEPROM type not compatible with VITA 57.1
fmc-delay-1ns-8cha#1
· opened
Mar 05, 2018
by
Dimitris Lampridis
bug
3
updated
Feb 12, 2019
Specification table reads 200 kSPS sample rate while the description shows 100 kSPS.
fmc-adc-100k16b8cha#16
· opened
Nov 17, 2010
by
Erik van der Bij
support
0
updated
Feb 12, 2019
Propogation delay of buffer in feedback loop of PLL
fmc-adc-100k16b8cha#11
· opened
Jul 27, 2011
by
Ross Millar
bug
0
updated
Feb 12, 2019
Schematics need clean-up and pass via design office
fmc-adc-100k16b8cha#9
· opened
Aug 31, 2011
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
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