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Pull-up resistors too strong
conv-ttl-blo#3
· opened
Oct 06, 2017
by
Denia Bouhired-Ferrag
feature
1
updated
Feb 12, 2019
PCB layout: share pads between pul-up and pull-down resistors
conv-ttl-blo#2
· opened
Oct 06, 2017
by
Denia Bouhired-Ferrag
feature
1
updated
Feb 12, 2019
Unnecessary pull-up resisors on flash chip
conv-ttl-blo#1
· opened
Oct 06, 2017
by
Denia Bouhired-Ferrag
bug
1
updated
Feb 12, 2019
IC11 separation
fmc-dio-5chttla#3
· opened
Jan 23, 2018
by
Piotr Miedzik
6
updated
Feb 12, 2019
Default FRU file
fmc-dio-5chttla#2
· opened
Jan 24, 2018
by
Piotr Miedzik
2
updated
Feb 12, 2019
EEPROM type not compatible with VITA 57.1
fmc-dio-5chttla#1
· opened
Mar 05, 2018
by
Dimitris Lampridis
0
updated
Feb 12, 2019
v4-dev - Topology Resolution Unit (TRU)
wr-switch-hdl#36
· opened
Mar 15, 2013
by
Maciej Lipinski
feature
0
updated
Feb 12, 2019
v4-dev - Time Aware Traffic Shaper (TATSU)
wr-switch-hdl#35
· opened
Mar 15, 2013
by
Maciej Lipinski
feature
0
updated
Feb 12, 2019
Unrecognized queue - prevent overwhelming
wr-switch-hdl#20
· opened
Feb 10, 2014
by
Maciej Lipinski
bug
0
updated
Feb 12, 2019
prio_override flag - non-coherent interpretation
wr-switch-hdl#17
· opened
May 26, 2014
by
Maciej Lipinski
bug
0
updated
Feb 12, 2019
VID for untagged frames in fast Match
wr-switch-hdl#16
· opened
Jun 04, 2014
by
Maciej Lipinski
bug
0
updated
Feb 12, 2019
Convert TAI to UTC
wr-cores#67
· opened
Sep 16, 2015
by
Benoit Rat
1
updated
Feb 12, 2019
WR streamers: State unused in xrx_streamer.vhd
wr-cores#41
· opened
May 26, 2017
by
Denia Bouhired-Ferrag
bug
0
updated
Feb 12, 2019
WR streamers: fixed latency implementation only works for one specific case
wr-cores#39
· opened
Jun 07, 2017
by
Denia Bouhired-Ferrag
bug
0
updated
Feb 12, 2019
WR Streamers testbench
wr-cores#38
· opened
Jun 21, 2017
by
Maciej Lipinski
bug
0
updated
Feb 12, 2019
WR streamers: Maximum number of words per frame
wr-cores#36
· opened
Jun 26, 2017
by
Denia Bouhired-Ferrag
feature
0
updated
Feb 12, 2019
Extension of WR Streamers testbenches to test 0xCAFE
wr-cores#16
· opened
Dec 08, 2017
by
Maciej Lipinski
feature
0
updated
Feb 12, 2019
UTC leap second registers
wr-cores#7
· opened
Dec 20, 2017
by
Grzegorz Daniluk
feature
1
updated
Feb 12, 2019
re-measure/calculate alpha parameter
wr-cores#1
· opened
Nov 22, 2018
by
Maciej Lipinski
feature
0
updated
Feb 12, 2019
Relations missing for VHDL package to be used in system verilog
hdl-make#20
· opened
Jun 01, 2016
by
Nicolas Chevillot
bug
6
updated
Feb 12, 2019
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