kernel/spec-i2c.c: copied from fine-delay-sw

This file comes from commit 2050aba of fine-delay-sw (actually,
any version is the same, as I'm removing load and save in the next commit).

Similarly, fd_main_regs.h are copied here, as missing the golden binary
i'm using the fine-delay one for a start.

kernel/hw/fd_main_regs.h

+/*
+  Register definitions for slave core: Fine Delay Main WB Slave
+
+  * File           : fd_main_regs.h
+  * Author         : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
+  * Created        : Mon May 21 20:09:50 2012
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_FD_MAIN_WISHBONE_SLAVE_WB
+#define __WBGEN2_REGDEFS_FD_MAIN_WISHBONE_SLAVE_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Reset Register */
+
+/* definitions for field: State of the reset Line of the FMC Card in reg: Reset Register */
+#define FD_RSTR_RST_FMC_MASK                  WBGEN2_GEN_MASK(0, 1)
+#define FD_RSTR_RST_FMC_SHIFT                 0
+#define FD_RSTR_RST_FMC_W(value)              WBGEN2_GEN_WRITE(value, 0, 1)
+#define FD_RSTR_RST_FMC_R(reg)                WBGEN2_GEN_READ(reg, 0, 1)
+
+/* definitions for field: State of the reset of the Fine Delay HDL Core in reg: Reset Register */
+#define FD_RSTR_RST_CORE_MASK                 WBGEN2_GEN_MASK(1, 1)
+#define FD_RSTR_RST_CORE_SHIFT                1
+#define FD_RSTR_RST_CORE_W(value)             WBGEN2_GEN_WRITE(value, 1, 1)
+#define FD_RSTR_RST_CORE_R(reg)               WBGEN2_GEN_READ(reg, 1, 1)
+
+/* definitions for field: Reset magic value in reg: Reset Register */
+#define FD_RSTR_LOCK_MASK                     WBGEN2_GEN_MASK(16, 16)
+#define FD_RSTR_LOCK_SHIFT                    16
+#define FD_RSTR_LOCK_W(value)                 WBGEN2_GEN_WRITE(value, 16, 16)
+#define FD_RSTR_LOCK_R(reg)                   WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: ID Register */
+
+/* definitions for register: Global Control Register */
+
+/* definitions for field: Bypass Hardware TDC/Delay Controller in reg: Global Control Register */
+#define FD_GCR_BYPASS                         WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Enable trigger input in reg: Global Control Register */
+#define FD_GCR_INPUT_EN                       WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: PLL Locked in reg: Global Control Register */
+#define FD_GCR_DDR_LOCKED                     WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Mezzanice Present in reg: Global Control Register */
+#define FD_GCR_FMC_PRESENT                    WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Timing Control Register */
+
+/* definitions for field: DMTD Clock Status in reg: Timing Control Register */
+#define FD_TCR_DMTD_STAT                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: WR Timing Enable in reg: Timing Control Register */
+#define FD_TCR_WR_ENABLE                      WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: WR Timing Locked in reg: Timing Control Register */
+#define FD_TCR_WR_LOCKED                      WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: WR Core Present in reg: Timing Control Register */
+#define FD_TCR_WR_PRESENT                     WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: WR Core Time Ready in reg: Timing Control Register */
+#define FD_TCR_WR_READY                       WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: WR Core Link Up in reg: Timing Control Register */
+#define FD_TCR_WR_LINK                        WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Capture Current Time in reg: Timing Control Register */
+#define FD_TCR_CAP_TIME                       WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: Set Current Time in reg: Timing Control Register */
+#define FD_TCR_SET_TIME                       WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for register: Time Register - TAI seconds (MSB) */
+
+/* definitions for register: Time Register - TAI seconds (LSB) */
+
+/* definitions for register: Time Register - sub-second 125 MHz clock cycles  */
+
+/* definitions for register: TDC Data Register */
+
+/* definitions for register: TDC control/status reg */
+
+/* definitions for field: Start TDC write in reg: TDC control/status reg */
+#define FD_TDCSR_WRITE                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Start TDC read in reg: TDC control/status reg */
+#define FD_TDCSR_READ                         WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Empty flag in reg: TDC control/status reg */
+#define FD_TDCSR_EMPTY                        WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Start enable in reg: TDC control/status reg */
+#define FD_TDCSR_STOP_EN                      WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: Start disable in reg: TDC control/status reg */
+#define FD_TDCSR_START_DIS                    WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: Stop enable in reg: TDC control/status reg */
+#define FD_TDCSR_START_EN                     WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Stop disable in reg: TDC control/status reg */
+#define FD_TDCSR_STOP_DIS                     WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: write 1: Pulse the Alutrigger line in reg: TDC control/status reg */
+#define FD_TDCSR_ALUTRIG                      WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for register: Calibration register */
+
+/* definitions for field: Triggers calibration pulses in reg: Calibration register */
+#define FD_CALR_CAL_PULSE                     WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: PPS Calibration output enable in reg: Calibration register */
+#define FD_CALR_CAL_PPS                       WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Triggers calibration pulses in reg: Calibration register */
+#define FD_CALR_CAL_DMTD                      WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Enable pulse generation in reg: Calibration register */
+#define FD_CALR_PSEL_MASK                     WBGEN2_GEN_MASK(3, 4)
+#define FD_CALR_PSEL_SHIFT                    3
+#define FD_CALR_PSEL_W(value)                 WBGEN2_GEN_WRITE(value, 3, 4)
+#define FD_CALR_PSEL_R(reg)                   WBGEN2_GEN_READ(reg, 3, 4)
+
+/* definitions for field: DMTD Feedback Channel Select in reg: Calibration register */
+#define FD_CALR_DMTD_FBSEL                    WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for field: DMTD Tag in reg: Calibration register */
+#define FD_CALR_DMTD_TAG_MASK                 WBGEN2_GEN_MASK(8, 23)
+#define FD_CALR_DMTD_TAG_SHIFT                8
+#define FD_CALR_DMTD_TAG_W(value)             WBGEN2_GEN_WRITE(value, 8, 23)
+#define FD_CALR_DMTD_TAG_R(reg)               WBGEN2_GEN_READ(reg, 8, 23)
+
+/* definitions for field: DMTD Tag Ready in reg: Calibration register */
+#define FD_CALR_DMTD_TAG_RDY                  WBGEN2_GEN_MASK(31, 1)
+
+/* definitions for register: Softpll Register */
+
+/* definitions for field: Frequency/Phase tag in reg: Softpll Register */
+#define FD_SPLLR_TAG_MASK                     WBGEN2_GEN_MASK(0, 20)
+#define FD_SPLLR_TAG_SHIFT                    0
+#define FD_SPLLR_TAG_W(value)                 WBGEN2_GEN_WRITE(value, 0, 20)
+#define FD_SPLLR_TAG_R(reg)                   WBGEN2_GEN_READ(reg, 0, 20)
+
+/* definitions for field: Tag Ready in reg: Softpll Register */
+#define FD_SPLLR_TAG_RDY                      WBGEN2_GEN_MASK(20, 1)
+
+/* definitions for field: Freq/Phase mode select in reg: Softpll Register */
+#define FD_SPLLR_MODE                         WBGEN2_GEN_MASK(21, 1)
+
+/* definitions for register: Softpll DAC Register */
+
+/* definitions for field: DAC Value in reg: Softpll DAC Register */
+#define FD_SDACR_DAC_VAL_MASK                 WBGEN2_GEN_MASK(0, 16)
+#define FD_SDACR_DAC_VAL_SHIFT                0
+#define FD_SDACR_DAC_VAL_W(value)             WBGEN2_GEN_WRITE(value, 0, 16)
+#define FD_SDACR_DAC_VAL_R(reg)               WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for register: Acam to Delay line fractional part Scale Factor Register */
+
+/* definitions for register: Acam Timestamp Merging Control Register */
+
+/* definitions for field: Wraparound Coarse Threshold in reg: Acam Timestamp Merging Control Register */
+#define FD_ATMCR_C_THR_MASK                   WBGEN2_GEN_MASK(0, 4)
+#define FD_ATMCR_C_THR_SHIFT                  0
+#define FD_ATMCR_C_THR_W(value)               WBGEN2_GEN_WRITE(value, 0, 4)
+#define FD_ATMCR_C_THR_R(reg)                 WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for field: Wraparound Fine Threshold in reg: Acam Timestamp Merging Control Register */
+#define FD_ATMCR_F_THR_MASK                   WBGEN2_GEN_MASK(4, 23)
+#define FD_ATMCR_F_THR_SHIFT                  4
+#define FD_ATMCR_F_THR_W(value)               WBGEN2_GEN_WRITE(value, 4, 23)
+#define FD_ATMCR_F_THR_R(reg)                 WBGEN2_GEN_READ(reg, 4, 23)
+
+/* definitions for register: Acam Start Offset Register */
+
+/* definitions for field: Start Offset in reg: Acam Start Offset Register */
+#define FD_ASOR_OFFSET_MASK                   WBGEN2_GEN_MASK(0, 23)
+#define FD_ASOR_OFFSET_SHIFT                  0
+#define FD_ASOR_OFFSET_W(value)               WBGEN2_GEN_WRITE(value, 0, 23)
+#define FD_ASOR_OFFSET_R(reg)                 WBGEN2_GEN_READ(reg, 0, 23)
+
+/* definitions for register: Raw Input Events Counter Register  */
+
+/* definitions for register: Tagged Input Events Counter Register  */
+
+/* definitions for register: Input Event Processing Delay Register */
+
+/* definitions for field: Reset stats in reg: Input Event Processing Delay Register */
+#define FD_IEPD_RST_STAT                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Processing delay in reg: Input Event Processing Delay Register */
+#define FD_IEPD_PDELAY_MASK                   WBGEN2_GEN_MASK(1, 8)
+#define FD_IEPD_PDELAY_SHIFT                  1
+#define FD_IEPD_PDELAY_W(value)               WBGEN2_GEN_WRITE(value, 1, 8)
+#define FD_IEPD_PDELAY_R(reg)                 WBGEN2_GEN_READ(reg, 1, 8)
+
+/* definitions for register: SPI Control Register */
+
+/* definitions for field: Data in reg: SPI Control Register */
+#define FD_SCR_DATA_MASK                      WBGEN2_GEN_MASK(0, 24)
+#define FD_SCR_DATA_SHIFT                     0
+#define FD_SCR_DATA_W(value)                  WBGEN2_GEN_WRITE(value, 0, 24)
+#define FD_SCR_DATA_R(reg)                    WBGEN2_GEN_READ(reg, 0, 24)
+
+/* definitions for field: Select DAC in reg: SPI Control Register */
+#define FD_SCR_SEL_DAC                        WBGEN2_GEN_MASK(24, 1)
+
+/* definitions for field: Select PLL in reg: SPI Control Register */
+#define FD_SCR_SEL_PLL                        WBGEN2_GEN_MASK(25, 1)
+
+/* definitions for field: Select GPIO in reg: SPI Control Register */
+#define FD_SCR_SEL_GPIO                       WBGEN2_GEN_MASK(26, 1)
+
+/* definitions for field: Ready flag in reg: SPI Control Register */
+#define FD_SCR_READY                          WBGEN2_GEN_MASK(27, 1)
+
+/* definitions for field: Clock Polarity in reg: SPI Control Register */
+#define FD_SCR_CPOL                           WBGEN2_GEN_MASK(28, 1)
+
+/* definitions for field: Transfer Start in reg: SPI Control Register */
+#define FD_SCR_START                          WBGEN2_GEN_MASK(29, 1)
+
+/* definitions for register: Reference Clock Rate Register */
+
+/* definitions for register: Timestamp Buffer Control Register */
+
+/* definitions for field: Channel Mask in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_CHAN_MASK_MASK               WBGEN2_GEN_MASK(0, 5)
+#define FD_TSBCR_CHAN_MASK_SHIFT              0
+#define FD_TSBCR_CHAN_MASK_W(value)           WBGEN2_GEN_WRITE(value, 0, 5)
+#define FD_TSBCR_CHAN_MASK_R(reg)             WBGEN2_GEN_READ(reg, 0, 5)
+
+/* definitions for field: Buffer enable in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_ENABLE                       WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Buffer purge in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_PURGE                        WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: Reset TS Sequence Numbers in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_RST_SEQ                      WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for field: Buffer full in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_FULL                         WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: Buffer empty in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_EMPTY                        WBGEN2_GEN_MASK(9, 1)
+
+/* definitions for field: Buffer entries count in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_COUNT_MASK                   WBGEN2_GEN_MASK(10, 12)
+#define FD_TSBCR_COUNT_SHIFT                  10
+#define FD_TSBCR_COUNT_W(value)               WBGEN2_GEN_WRITE(value, 10, 12)
+#define FD_TSBCR_COUNT_R(reg)                 WBGEN2_GEN_READ(reg, 10, 12)
+
+/* definitions for field: RAW readout mode enable in reg: Timestamp Buffer Control Register */
+#define FD_TSBCR_RAW                          WBGEN2_GEN_MASK(22, 1)
+
+/* definitions for register: Timestamp Buffer Interrupt Register */
+
+/* definitions for field: IRQ timeout [milliseconds] in reg: Timestamp Buffer Interrupt Register */
+#define FD_TSBIR_TIMEOUT_MASK                 WBGEN2_GEN_MASK(0, 10)
+#define FD_TSBIR_TIMEOUT_SHIFT                0
+#define FD_TSBIR_TIMEOUT_W(value)             WBGEN2_GEN_WRITE(value, 0, 10)
+#define FD_TSBIR_TIMEOUT_R(reg)               WBGEN2_GEN_READ(reg, 0, 10)
+
+/* definitions for field: Interrupt threshold in reg: Timestamp Buffer Interrupt Register */
+#define FD_TSBIR_THRESHOLD_MASK               WBGEN2_GEN_MASK(10, 12)
+#define FD_TSBIR_THRESHOLD_SHIFT              10
+#define FD_TSBIR_THRESHOLD_W(value)           WBGEN2_GEN_WRITE(value, 10, 12)
+#define FD_TSBIR_THRESHOLD_R(reg)             WBGEN2_GEN_READ(reg, 10, 12)
+
+/* definitions for register: Timestamp Buffer Readout Seconds Register (MSB) */
+
+/* definitions for register: Timestamp Buffer Readout Seconds Register (LSB) */
+
+/* definitions for register: Timestamp Buffer Readout Cycles Register */
+
+/* definitions for register: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
+
+/* definitions for field: Channel ID in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
+#define FD_TSBR_FID_CHANNEL_MASK              WBGEN2_GEN_MASK(0, 4)
+#define FD_TSBR_FID_CHANNEL_SHIFT             0
+#define FD_TSBR_FID_CHANNEL_W(value)          WBGEN2_GEN_WRITE(value, 0, 4)
+#define FD_TSBR_FID_CHANNEL_R(reg)            WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for field: Fine Value [in phase units] in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
+#define FD_TSBR_FID_FINE_MASK                 WBGEN2_GEN_MASK(4, 12)
+#define FD_TSBR_FID_FINE_SHIFT                4
+#define FD_TSBR_FID_FINE_W(value)             WBGEN2_GEN_WRITE(value, 4, 12)
+#define FD_TSBR_FID_FINE_R(reg)               WBGEN2_GEN_READ(reg, 4, 12)
+
+/* definitions for field: Timestamp Sequence ID in reg: Timestamp Buffer Readout Fine / Channel / Seq ID Register */
+#define FD_TSBR_FID_SEQID_MASK                WBGEN2_GEN_MASK(16, 16)
+#define FD_TSBR_FID_SEQID_SHIFT               16
+#define FD_TSBR_FID_SEQID_W(value)            WBGEN2_GEN_WRITE(value, 16, 16)
+#define FD_TSBR_FID_SEQID_R(reg)              WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: I2C bitbanged IO register */
+
+/* definitions for field: SCL Line out in reg: I2C bitbanged IO register */
+#define FD_I2CR_SCL_OUT                       WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: SDA Line out in reg: I2C bitbanged IO register */
+#define FD_I2CR_SDA_OUT                       WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: SCL Line in in reg: I2C bitbanged IO register */
+#define FD_I2CR_SCL_IN                        WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
+#define FD_I2CR_SDA_IN                        WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for register: Test/Debug register 1 */
+
+/* definitions for field: VCXO Frequency in reg: Test/Debug register 1 */
+#define FD_TDER1_VCXO_FREQ_MASK               WBGEN2_GEN_MASK(0, 32)
+#define FD_TDER1_VCXO_FREQ_SHIFT              0
+#define FD_TDER1_VCXO_FREQ_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
+#define FD_TDER1_VCXO_FREQ_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: Test/Debug register 1 */
+
+/* definitions for field: Peltier PWM drive in reg: Test/Debug register 1 */
+#define FD_TDER2_PELT_DRIVE_MASK              WBGEN2_GEN_MASK(0, 32)
+#define FD_TDER2_PELT_DRIVE_SHIFT             0
+#define FD_TDER2_PELT_DRIVE_W(value)          WBGEN2_GEN_WRITE(value, 0, 32)
+#define FD_TDER2_PELT_DRIVE_R(reg)            WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: Timestamp Buffer Debug Values Register */
+
+/* definitions for register: Timestamp Buffer Advance Register */
+
+/* definitions for field: Advance buffer readout in reg: Timestamp Buffer Advance Register */
+#define FD_TSBR_ADVANCE_ADV                   WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt disable register */
+
+/* definitions for field: TS Buffer not empty. in reg: Interrupt disable register */
+#define FD_EIC_IDR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: DMTD Softpll interrupt in reg: Interrupt disable register */
+#define FD_EIC_IDR_DMTD_SPLL                  WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Sync Status Changed in reg: Interrupt disable register */
+#define FD_EIC_IDR_SYNC_STATUS                WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for register: Interrupt enable register */
+
+/* definitions for field: TS Buffer not empty. in reg: Interrupt enable register */
+#define FD_EIC_IER_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: DMTD Softpll interrupt in reg: Interrupt enable register */
+#define FD_EIC_IER_DMTD_SPLL                  WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Sync Status Changed in reg: Interrupt enable register */
+#define FD_EIC_IER_SYNC_STATUS                WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for register: Interrupt mask register */
+
+/* definitions for field: TS Buffer not empty. in reg: Interrupt mask register */
+#define FD_EIC_IMR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: DMTD Softpll interrupt in reg: Interrupt mask register */
+#define FD_EIC_IMR_DMTD_SPLL                  WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Sync Status Changed in reg: Interrupt mask register */
+#define FD_EIC_IMR_SYNC_STATUS                WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for register: Interrupt status register */
+
+/* definitions for field: TS Buffer not empty. in reg: Interrupt status register */
+#define FD_EIC_ISR_TS_BUF_NOTEMPTY            WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: DMTD Softpll interrupt in reg: Interrupt status register */
+#define FD_EIC_ISR_DMTD_SPLL                  WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Sync Status Changed in reg: Interrupt status register */
+#define FD_EIC_ISR_SYNC_STATUS                WBGEN2_GEN_MASK(2, 1)
+/* [0x0]: REG Reset Register */
+#define FD_REG_RSTR 0x00000000
+/* [0x4]: REG ID Register */
+#define FD_REG_IDR 0x00000004
+/* [0x8]: REG Global Control Register */
+#define FD_REG_GCR 0x00000008
+/* [0xc]: REG Timing Control Register */
+#define FD_REG_TCR 0x0000000c
+/* [0x10]: REG Time Register - TAI seconds (MSB) */
+#define FD_REG_TM_SECH 0x00000010
+/* [0x14]: REG Time Register - TAI seconds (LSB) */
+#define FD_REG_TM_SECL 0x00000014
+/* [0x18]: REG Time Register - sub-second 125 MHz clock cycles  */
+#define FD_REG_TM_CYCLES 0x00000018
+/* [0x1c]: REG TDC Data Register */
+#define FD_REG_TDR 0x0000001c
+/* [0x20]: REG TDC control/status reg */
+#define FD_REG_TDCSR 0x00000020
+/* [0x24]: REG Calibration register */
+#define FD_REG_CALR 0x00000024
+/* [0x28]: REG Softpll Register */
+#define FD_REG_SPLLR 0x00000028
+/* [0x2c]: REG Softpll DAC Register */
+#define FD_REG_SDACR 0x0000002c
+/* [0x30]: REG Acam to Delay line fractional part Scale Factor Register */
+#define FD_REG_ADSFR 0x00000030
+/* [0x34]: REG Acam Timestamp Merging Control Register */
+#define FD_REG_ATMCR 0x00000034
+/* [0x38]: REG Acam Start Offset Register */
+#define FD_REG_ASOR 0x00000038
+/* [0x3c]: REG Raw Input Events Counter Register  */
+#define FD_REG_IECRAW 0x0000003c
+/* [0x40]: REG Tagged Input Events Counter Register  */
+#define FD_REG_IECTAG 0x00000040
+/* [0x44]: REG Input Event Processing Delay Register */
+#define FD_REG_IEPD 0x00000044
+/* [0x48]: REG SPI Control Register */
+#define FD_REG_SCR 0x00000048
+/* [0x4c]: REG Reference Clock Rate Register */
+#define FD_REG_RCRR 0x0000004c
+/* [0x50]: REG Timestamp Buffer Control Register */
+#define FD_REG_TSBCR 0x00000050
+/* [0x54]: REG Timestamp Buffer Interrupt Register */
+#define FD_REG_TSBIR 0x00000054
+/* [0x58]: REG Timestamp Buffer Readout Seconds Register (MSB) */
+#define FD_REG_TSBR_SECH 0x00000058
+/* [0x5c]: REG Timestamp Buffer Readout Seconds Register (LSB) */
+#define FD_REG_TSBR_SECL 0x0000005c
+/* [0x60]: REG Timestamp Buffer Readout Cycles Register */
+#define FD_REG_TSBR_CYCLES 0x00000060
+/* [0x64]: REG Timestamp Buffer Readout Fine / Channel / Seq ID Register */
+#define FD_REG_TSBR_FID 0x00000064
+/* [0x68]: REG I2C bitbanged IO register */
+#define FD_REG_I2CR 0x00000068
+/* [0x6c]: REG Test/Debug register 1 */
+#define FD_REG_TDER1 0x0000006c
+/* [0x70]: REG Test/Debug register 1 */
+#define FD_REG_TDER2 0x00000070
+/* [0x74]: REG Timestamp Buffer Debug Values Register */
+#define FD_REG_TSBR_DEBUG 0x00000074
+/* [0x78]: REG Timestamp Buffer Advance Register */
+#define FD_REG_TSBR_ADVANCE 0x00000078
+/* [0x80]: REG Interrupt disable register */
+#define FD_REG_EIC_IDR 0x00000080
+/* [0x84]: REG Interrupt enable register */
+#define FD_REG_EIC_IER 0x00000084
+/* [0x88]: REG Interrupt mask register */
+#define FD_REG_EIC_IMR 0x00000088
+/* [0x8c]: REG Interrupt status register */
+#define FD_REG_EIC_ISR 0x0000008c
+#endif

kernel/spec-i2c.c

+/*
+ * I2C access (on-board EEPROM)
+ *
+ * Copyright (C) 2012 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ * Author: Alessandro Rubini <rubini@gnudd.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * version 2 as published by the Free Software Foundation or, at your
+ * option, any later version.
+ */
+#include <linux/moduleparam.h>
+#include <linux/io.h>
+#include <linux/time.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/firmware.h>
+#include <linux/jhash.h>
+#include "spec.h"
+#include "fine-delay.h"
+#include "hw/fd_main_regs.h"
+
+/* The eeprom is at address 0x50, and the structure lives at 6kB */
+#define I2C_ADDR 0x50
+#define I2C_OFFSET (6*1024)
+
+/* At factory config time, it's possible to load a file and/or write eeprom */
+static char *calibration_load;
+static int calibration_save;
+static int calibration_check;
+static int calibration_default;
+
+module_param(calibration_load, charp, 0444);
+module_param(calibration_default, int, 0444);
+module_param(calibration_save, int, 0444);
+module_param(calibration_check, int, 0444);
+
+/* Stupid dumping tool */
+static void dumpstruct(char *name, void *ptr, int size)
+{
+	int i;
+	unsigned char *p = ptr;
+
+	printk("%s: (size 0x%x)\n", name, size);
+	for (i = 0; i < size; ) {
+		printk("%02x", p[i]);
+		i++;
+		printk(i & 3 ? " " : i & 0xf ? "  " : "\n");
+	}
+	if (i & 0xf)
+		printk("\n");
+}
+
+static void set_sda(struct spec_fd *fd, int val)
+{
+	uint32_t reg;
+
+	reg = fd_readl(fd, FD_REG_I2CR) & ~FD_I2CR_SDA_OUT;
+	if (val)
+		reg |= FD_I2CR_SDA_OUT;
+	fd_writel(fd, reg, FD_REG_I2CR);
+}
+
+static void set_scl(struct spec_fd *fd, int val)
+{
+	uint32_t reg;
+
+	reg = fd_readl(fd, FD_REG_I2CR) & ~FD_I2CR_SCL_OUT;
+	if (val)
+		reg |= FD_I2CR_SCL_OUT;
+	fd_writel(fd, reg, FD_REG_I2CR);
+}
+
+static int get_sda(struct spec_fd *fd)
+{
+	return fd_readl(fd, FD_REG_I2CR) & FD_I2CR_SDA_IN ? 1 : 0;
+};
+
+static void mi2c_start(struct spec_fd *fd)
+{
+	set_sda(fd, 0);
+	set_scl(fd, 0);
+}
+
+static void mi2c_stop(struct spec_fd *fd)
+{
+	set_sda(fd, 0);
+	set_scl(fd, 1);
+	set_sda(fd, 1);
+}
+
+int mi2c_put_byte(struct spec_fd *fd, int data)
+{
+	int i;
+	int ack;
+
+	for (i = 0; i < 8; i++, data<<=1) {
+		set_sda(fd, data & 0x80);
+		set_scl(fd, 1);
+		set_scl(fd, 0);
+	}
+
+	set_sda(fd, 1);
+	set_scl(fd, 1);
+
+	ack = get_sda(fd);
+
+	set_scl(fd, 0);
+	set_sda(fd, 0);
+
+	return ack ? -EIO : 0; /* ack low == success */
+}
+
+int mi2c_get_byte(struct spec_fd *fd, unsigned char *data, int sendack)
+{
+	int i;
+	int indata = 0;
+
+	/* assert: scl is low */
+	set_scl(fd, 0);
+	set_sda(fd, 1);
+	for (i = 0; i < 8; i++) {
+		set_scl(fd, 1);
+		indata <<= 1;
+		if (get_sda(fd))
+			indata |= 0x01;
+		set_scl(fd, 0);
+	}
+
+	set_sda(fd, (sendack ? 0 : 1));
+	set_scl(fd, 1);
+	set_scl(fd, 0);
+	set_sda(fd, 0);
+
+	*data= indata;
+	return 0;
+}
+
+void mi2c_init(struct spec_fd *fd)
+{
+	set_scl(fd, 1);
+	set_sda(fd, 1);
+}
+
+void mi2c_scan(struct spec_fd *fd)
+{
+	int i;
+	for(i = 0; i < 256; i += 2) {
+		mi2c_start(fd);
+		if(!mi2c_put_byte(fd, i))
+			pr_info("%s: Found i2c device at 0x%x\n",
+			       KBUILD_MODNAME, i >> 1);
+		mi2c_stop(fd);
+	}
+}
+
+/* FIXME: this is very inefficient: read several bytes in a row instead */
+int fd_eeprom_read(struct spec_fd *fd, int i2c_addr, uint32_t offset,
+		void *buf, size_t size)
+{
+	int i;
+	uint8_t *buf8 = buf;
+	unsigned char c;
+
+	for(i = 0; i < size; i++) {
+		mi2c_start(fd);
+		if(mi2c_put_byte(fd, i2c_addr << 1) < 0) {
+			mi2c_stop(fd);
+			return -EIO;
+		}
+
+		mi2c_put_byte(fd, (offset >> 8) & 0xff);
+		mi2c_put_byte(fd, offset & 0xff);
+		offset++;
+		mi2c_stop(fd);
+		mi2c_start(fd);
+		mi2c_put_byte(fd, (i2c_addr << 1) | 1);
+		mi2c_get_byte(fd, &c, 0);
+		*buf8++ = c;
+		mi2c_stop(fd);
+	}
+	return size;
+}
+
+int fd_eeprom_write(struct spec_fd *fd, int i2c_addr, uint32_t offset,
+		 void *buf, size_t size)
+{
+	int i, busy;
+	uint8_t *buf8 = buf;
+
+	for(i = 0; i < size; i++) {
+		mi2c_start(fd);
+
+		if(mi2c_put_byte(fd, i2c_addr << 1) < 0) {
+			mi2c_stop(fd);
+			return -1;
+		}
+		mi2c_put_byte(fd, (offset >> 8) & 0xff);
+		mi2c_put_byte(fd, offset & 0xff);
+		mi2c_put_byte(fd, *buf8++);
+		offset++;
+		mi2c_stop(fd);
+
+		do { /* wait until the chip becomes ready */
+			mi2c_start(fd);
+			busy = mi2c_put_byte(fd, i2c_addr << 1);
+			mi2c_stop(fd);
+		} while(busy);
+	}
+	return size;
+}
+
+/* The user requested to load the configuration from file */
+static void fd_i2c_load_calib(struct spec_fd *fd,
+			      struct fd_calib_on_eeprom *cal_ee)
+{
+	const struct firmware *fw;
+	struct pci_dev *pdev = fd->spec->pdev;
+	char *fwname, *newname = NULL;
+	int err;
+
+	/* the calibration_load string is known to be valid */
+
+	fwname = calibration_load;
+	err = request_firmware(&fw, calibration_load, &pdev->dev);
+	if (err < 0) {
+
+		dev_warn(&pdev->dev, "can't load \"%s\"\n",
+			    calibration_load);
+		newname = kasprintf(GFP_KERNEL, "%s-%02x%02x\n",
+				    calibration_load,
+				    pdev->bus->number, pdev->devfn);
+		err = request_firmware(&fw, newname, &pdev->dev);
+		if (err < 0) {
+			dev_warn(&pdev->dev, "can't load \"%s\"\n",
+				    newname);
+		}
+		fwname = newname;
+	}
+	if (err < 0) {
+		kfree(newname);
+		return;
+	}
+	if (fw->size != sizeof(cal_ee->calib)) {
+		dev_warn(&pdev->dev, "File \"%s\" has wrong size\n",
+			    fwname);
+	} else {
+		memcpy(&cal_ee->calib, fw->data, fw->size);
+		dev_info(&pdev->dev, "calibration data loaded from \"%s\"\n",
+			 fwname);
+	}
+	release_firmware(fw);
+	kfree(newname);
+	return;
+}
+
+
+int fd_i2c_init(struct spec_fd *fd)
+{
+	struct fd_calib_on_eeprom *cal_ee;
+	u32 hash;
+	int i;
+
+	mi2c_scan(fd);
+
+	if (0) {
+		/* Temporary - testing: read and write some stuff */
+		u8 buf[8];
+		int i;
+
+		fd_eeprom_read(fd, I2C_ADDR, I2C_OFFSET, buf, 8);
+		printk("read: ");
+		for (i = 0; i < 8; i++)
+			printk("%02x%c", buf[i], i==7 ? '\n' : ' ');
+
+		get_random_bytes(buf, 8);
+		printk("write: ");
+		for (i = 0; i < 8; i++)
+			printk("%02x%c", buf[i], i==7 ? '\n' : ' ');
+		fd_eeprom_write(fd, I2C_ADDR, I2C_OFFSET, buf, 8);
+	}
+
+	/* Retrieve and validate the calibration */
+	cal_ee = kzalloc(sizeof(*cal_ee), GFP_KERNEL);
+	if (!cal_ee)
+		return -ENOMEM;
+	i = fd_eeprom_read(fd, I2C_ADDR, I2C_OFFSET, cal_ee, sizeof(*cal_ee));
+	if (i != sizeof(*cal_ee)) {
+		pr_err("%s: cannot read_eeprom\n", __func__);
+		goto load;
+	}
+	if (calibration_check)
+		dumpstruct("Calibration data from eeprom:", cal_ee,
+			   sizeof(*cal_ee));
+
+	hash = jhash(&cal_ee->calib, sizeof(cal_ee->calib), 0);
+
+	/* FIXME: this is original-endian only (little endian I fear) */
+	if ((cal_ee->size != sizeof(cal_ee->calib))
+	    || (cal_ee->hash != hash)
+	    || (cal_ee->version != 1)) {
+		pr_err("%s: calibration on eeprom is invalid\n", __func__);
+		goto load;
+	}
+	if (!calibration_default)
+		fd->calib = cal_ee->calib; /* override compile-time default */
+
+load:
+	cal_ee->calib = fd->calib;
+
+	if (calibration_load)
+		fd_i2c_load_calib(fd, cal_ee);
+
+	/* Fix the local copy, for verification and maybe saving */
+	cal_ee->hash = jhash(&cal_ee->calib, sizeof(cal_ee->calib), 0);
+	cal_ee->size = sizeof(cal_ee->calib);
+	cal_ee->version = 1;
+
+	if (calibration_save) {
+		i = fd_eeprom_write(fd, I2C_ADDR, I2C_OFFSET, cal_ee,
+				    sizeof(*cal_ee));
+		if (i != sizeof(*cal_ee)) {
+			pr_err("%s: error in writing calibration to eeprom\n",
+			       __func__);
+		} else {
+			pr_info("%s: saved calibration to eeprom\n", __func__);
+		}
+	}
+	if (calibration_check)
+		dumpstruct("Current calibration data:", cal_ee,
+			   sizeof(*cal_ee));
+	kfree(cal_ee);
+	return 0;
+}
+
+void fd_i2c_exit(struct spec_fd *fd)
+{
+	/* nothing to do */
+}
+