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Created with Raphaël 2.2.016Oct1521Sep17121174331Aug301097627Jul232019Dec181124Nov8Mar17Jan22May19181229Apr1410974326Mar25201820Feb4Nov14Aug14Jul8725Jun23201817131254329May27261914925Apr2310Feb75431Jan302320171428Nov2220137614Oct109230Sep27119Aug526Jul1817125221Jun201422May151430Apr291Oct14Sep527Aug821Jun20141118May16Nov118124Oct2018116423Sep3Aug29Jul2118119MarAdd build_wbgen.sh script.proposed_masterproposed_masterreg_ctrl: add a register to reduce timing pressure.top/spec: enable FIFO readout following addition of the corresponding generictom-sep21tom-sep21hdl: clean up rewritten start retrigger unittestbench: initial version of SPEC tbtestbench: crude ACAM I-mode SV modelfmc_tdc_core: rewrite the bloody f****ing crap called 'start_retrigger_block' (wip)hdl: change TEST1 register layouthdl: make FIFO readout and EIC optionalhdl: post-merge fixes, brought back direct readout interfacetom-tmp-sep17tom-tmp-sep17Merge branch 'tom-sep16' into tom-tmp-sep17acam_databus_interface: remove unused portsupdated submodulestom-sep16tom-sep16spec: relaxed FIFO timingfmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bughdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface insteadacam_databus_interface: fix combinatorial loop on reset (a typo in fact)rtl/data_engine: don't use possibly metastable ef1_meta/ef2_meta signals.rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timingsyn/spec: updated ISE projecttom-sep11tom-sep11top/spec: re-enabled WR support, signal integrity improvementsrtl: replace Sockit onewire master with a hardware DS18xx interface, clean up core top levelrtl: store debug metadata in upper 20 bits of frac field, added raw readout mode for debuggingrtl: clean up debug metadata and pass it to the DMA enginertl/leds_manager: adapt to new readout model and simplify codertl/data_formatting: clean up temporary debugging codertl/data_engine: don't use possibly metastable ef1_meta/ef2_meta signals.rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timingFix data formatting (incorrect timestamp).fmc_tdc_core: fix 131us timestamp errortom-arith-fix-s…tom-arith-fix-sep07Fix indentation.ip_cores: updated general-cores to latest versiontom-dma-sep04tom-dma-sep04syn: updated ISE projectrtl: added raw timestamp readout modertl: use the real (HW postprocessed) timestamp for writing the DMA bufferrtl: fixed arithmetic errors in tdc_ts_addsubfmc_tdc_direct_readout: write all signals in sync to the fifo.data_formatting: minor refactoring.leds_manager: fix channel handling and simplify code.spec: removed debugging ports from the gennum coretom-dma-aug31tom-dma-aug31