fix project and i2c bugs

config/ise14/sp601/coregen.cgp

@@ -2,8 +2,8 @@ SET busformat = BusFormatAngleBracketNotRipped
 SET designentry = VHDL
 SET device = xc6slx16
 SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
+SET flowvendor = Other
 SET package = csg324
 SET speedgrade = -3
-SET verilogsim = true
+SET verilogsim = false
 SET vhdlsim = true

hdl/common/i2c_master_rtl.vhd

@@ -91,7 +91,7 @@ BEGIN
         
   
   ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
-  ipbus_o.ipb_err <= '1'; -- never return an error.
+  ipbus_o.ipb_err <= '0'; -- never return an error.
   
 END ARCHITECTURE rtl;
 

hdl/common/serdesCalibrateFSM_rtl.vhd

@@ -25,7 +25,7 @@
 -------------------------------------------------------------------------------
 --! @todo Implement a periodic calibration sequence\n
 --! <another thing to do> \n
--
+
   LIBRARY ieee;
 USE ieee.std_logic_1164.all;