Checking in modified build scripts (*.tcl), more work on simulation ( test-bench, pulse generator )
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- Introduction.markdown 3 additions, 1 deletionIntroduction.markdown
- README.markdown 0 additions, 44 deletionsREADME.markdown
- config/ise14/sp601/build_bitstream.tcl 1 addition, 1 deletionconfig/ise14/sp601/build_bitstream.tcl
- config/ise14/sp601/setup_project.tcl 15 additions, 6 deletionsconfig/ise14/sp601/setup_project.tcl
- config/ise14/sp605/build_bitstream.tcl 1 addition, 1 deletionconfig/ise14/sp605/build_bitstream.tcl
- config/ise14/sp605/setup_project.tcl 12 additions, 5 deletionsconfig/ise14/sp605/setup_project.tcl
- hdl/common/IPBusInterface_rtl.vhd 3 additions, 5 deletionshdl/common/IPBusInterface_rtl.vhd
- hdl/common/clocks_s6_extphy.vhd 2 additions, 1 deletionhdl/common/clocks_s6_extphy.vhd
- hdl/common/counterWithReset_rtl.vhd 1 addition, 1 deletionhdl/common/counterWithReset_rtl.vhd
- hdl/common/dualSERDES_1to4_rtl.vhd 43 additions, 40 deletionshdl/common/dualSERDES_1to4_rtl.vhd
- hdl/common/eventBuffer_rtl.vhd 10 additions, 4 deletionshdl/common/eventBuffer_rtl.vhd
- hdl/common/ipbus_addr_decode.vhd 0 additions, 2 deletionshdl/common/ipbus_addr_decode.vhd
- hdl/common/ipbus_ver.vhd 1 addition, 1 deletionhdl/common/ipbus_ver.vhd
- hdl/common/logic_clocks_rtl.vhd 73 additions, 90 deletionshdl/common/logic_clocks_rtl.vhd
- hdl/common/triggerInputs_rtl.vhd 80 additions, 21 deletionshdl/common/triggerInputs_rtl.vhd
- hdl/test/clock_divider_s6.v 2 additions, 1 deletionhdl/test/clock_divider_s6.v
- hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd 3 additions, 0 deletionshdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
- hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd 4 additions, 4 deletionshdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
- scripts/FmcTluI2c.py 21 additions, 7 deletionsscripts/FmcTluI2c.py
- scripts/aida_mini_tlu_addr_map.txt 5 additions, 1 deletionscripts/aida_mini_tlu_addr_map.txt
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