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The uTCA RTM 8 SFP is module equipped with 8 SFP cages and a clock distribution network. It is compatible with AFC and future projects such as Kintex-based AFC and WR MCH. The module is compliant with DESY RTM class D1.3

E-bone first aims at interfacing an FPGA based PCIe Endpoint core to a collection of other cores. The E-bone release contains a number of general purpose cores within that scope. E-bone specifications cater for both a Control Interconnect and a Fast Transmitter. The Control Interconnect defines a 32 bit wide interconnection between a number of masters and slaves. The Fast Transmitter is a one way path (up to 256 bit wide) aiming at dumping large data sets to the root complex. E-bone is nevertheless not restricted to PCIe interfacing and may be used for developing sub-systems in others environments.

More info at the Wiki page

The spec-box-1n allows to use a SPEC FMC carrier in stand-alone mode, not plugged inside a PC. An external 12 volt supply should be used to power the box. There is no forced ventilation in the box. More info at the Wiki page

The spec-box-3n allows to use up to three SPEC FMC carriers in stand-alone mode, not plugged inside a PC. An internal 230V supply module powers the SPEC boards. The box contains fans to cool the cards. More info at the Wiki page

The AMC micro backplane enables stand-alone operation of an AMC FMC carrier or any other AMC board. It has 4 SFP connectors, 2 QSFP cages, 8 trigger I/O routed to the MLVDS ports and power entry. *Superseded by the project amc-carrier-2-sl*

The image processing library offers multiple cores for on-chip vision-feature extraction. HDL modules are provided in different languages such as Handel-C or VHDL and applicable to various embedded and reconfigurable devices. They can be of interest for applications such as particle tracking, analysis of fluid dynamics, artificial vision for robotics, or object recognition.

Stereo cores process a 640x480 video pair sequence and estimate depth in the scene (fixed point Q7.4) up to 32 fps. A Lucas-Kanade gradient-based and a phase-based Handel-C implementations are provided. They also include a previous calibration stage.

Optical flow cores process a 640x480 video sequence and estimate direction and speed of the objects in the scene (fixed-point Q7.4) up to 32 fps. A Lucas-Kanade gradient-based and a phase-based Handel-C implementations are provided.

Local image descriptors are calculated for every 800x600 image up to 36 fps. All implemented in Handel-C, they provide energy with unsigned 8 bit fixed-point precision, as well as phase and orientation with Q7.2. The implementation is based on a multi-oriented bank of Gabor filters.

FMC DTX 4CHA is a four channel differential line driver on an FMC. Each channel is driven by a CLC006 IC with max data rate 400 Mb/s. Connector type: LEMO EPG.00.302.NLN.

More info at the Wiki page

FMC 4 channel Serial link transceiver with differential LEMO connectors. Each channel has a MAX3441EESA+ transceiver which follows the RS485 standard. More info at the Wiki page

Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.

This project presents an FPGA architecture for the computation of visual attention based on the combination of a bottom-up saliency and a top-down task-dependent modulation streams. The bottom-up stream is deployed including optical flow, local energy, red-green and blue-yellow color opponencies, and different local orientation maps. The final saliency is modulated by two highlevel features: optical flow and disparity. The architecture include some feedback masks to adapt the weights of the features that are part of the bottom-up stream, depending on the specific target application. The target applications are ADAS (Advanced Driving Assistance Systems), video surveillance, robotics, etc...

The CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page

AMC FMC Carrier with Kintex is designed to support FMC boards. Equiped in Xilinx Kintex-7 FPGA. It allows to connect clock source to any clock input More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

Hardware design of FMC ADC 100M 14b 4cha. Includes schematics, PCB layout and manufacturing files.

Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.

Production and functional tests for FMC ADC 100M 14b 4cha.

A fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page