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The OpenDSO is a bench top oscilloscope, built on top of an extensible Zynq-based platform. Features: 2x100 MS/s (basic frontend), extendable to 4x1GS/s or 2x2GS/s; Zynq 7000 FPGA, 512 MB RAM; 8" multitouch display with Qt GUI

OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page

Neo51 is an open source hardware based on 89V51 microcontroller. It has a dual mode feature selectable via DIP switch supporting arduino hardware compatible ports and the legacy 8051 ports.

WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems. Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for the exchange of data between their sensors and actuators and the control and supervision level. With Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.

The insourcing project has started with , a rad-tol FPGA that acts as an agent in the communication over the WorldFIP fieldbus.

nanoFIP project details, specifications, design and users information

In view of reorganizing the project, the nanoFIP project contains a copy of the CERNFIP wiki pages, Documents and Issues made on 24 March 2015

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.

nanoFIPdiag is a WorldFIP node dedicated to monitoring and diagnostics. It uses the nanoFIP chip in stand-alone mode and echoes the received data (through hardwired contacts it copies the received payload to the produced one). The module is designed to be radiation-tolerant

The Multigap RPC is a high precision timing and tracking detector with an active area of 25.6cm x 18.2cm and readout with 24 strips. Charged particles ionise gas in gaps between glass plates in a stack. A large electric field causes small avalanches of ionisation in each gap. The moving charges are picked up on readout strips and the timing of the charge deposition is to be read out on each side of each strip. The differential timing of the ionisation reveals the position along the strip and the precise arrival time of the particle. Multiple MRPCs can be used to measure particle time of flight (ToF). This design is based on the ALICE ToF detector and was built for the Beamline for Schools project. More info at the Wiki page

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

A plug&play mini-module for flexible White Rabbit integration. The SFP fibre-optic module should be implemented on the carrier board. More info at the Wiki page

Yocto Project / OpenEmbedded meta layer supporting the use of the Simple PCIe Carrier (SPEC) in x86 and x86-64 embedded Linux hosts. It features:

SPEC software (kernel, userspace, library, gateware) White Rabbit Interface Card support. White Rabbit Starting Kit demos. Getting started with the SPEC demos (python, gateware) Ready to go minimal and sato image recipes.

MasterFIP is an Open Hardware implementation of a WorldFIP master node.

Production and functional tests for the MasterFIP.

Software to support the MasterFIP, including Linux device driver, library and test program.

FMC WorldFIP is an interface card for the WorldFIP network in an LPC FMC form-factor. The hardware is described in the FMC WorldFIP project.

Gateware (HDL design) for MasterFIP.

Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.

An LPC FMC board which seeks to distribute digital I/O. It is designed to operate at least at 10 MHz, however a better design could allow this board to operate at much higher frequencies. This board is compatible with "PMOD" Connectors.

Local image descriptors are calculated for every 800x600 image up to 36 fps. All implemented in Handel-C, they provide energy with unsigned 8 bit fixed-point precision, as well as phase and orientation with Q7.2. The implementation is based on a multi-oriented bank of Gabor filters.

LIST is a trigger distribution system based on White Rabbit. It can receive a trigger from a “cloud” of devices and distribute it to all relevant devices to for example freeze their acquisition buffers. The latency between reception and transmission of a trigger is done with a low and notably fixed latency, with an accuracy of better than 1 ns. The hardware of the LIST nodes is based on the SVEC FMC carrier equipped with a FMC TDC mezzanine and a Fine Delay mezzanine. More info at the Wiki page