Explore projects

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

An LPC FMC board which seeks to distribute digital I/O. It is designed to operate at least at 10 MHz, however a better design could allow this board to operate at much higher frequencies. This board is compatible with "PMOD" Connectors.

We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus.

A level conversion board in VME64x double-height form factor between TTL and RS485. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics. More info at the Wiki page

Hardware designs for ROBIN-NP project.

Firmware for ROBIN-NP project.

Software for ROBIN-NP project.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

A simple 4-lane PXIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Labview driver available for Fine Delay and TDC mezzanines. More info at the Wiki page

The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: /-50mV,/-0.5V, /-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of/- 5V that is independent on the chosen gain range.

A simple card that measures temperatures using low cost external Silicon sensors (just ordinary bipolar transistors). On the front panel it has 8 mini-jack connectors to quickly rearrange the setup. We use this kind of the cards for measurement of the temperature distribution of key components on PCBs. The card has also application in our GEM detector readout system to monitor temperatures inside the detector box - it is attached to the rear transition module with an FMC connector. The card uses only an I2C interface which can be connected to the I2C bus of the card or to the LA lanes.

FMC carrier equipped with a Power PC embedded processor. In addition to the SPEC it has 2 gigabit Ethernet ports, one mini PCIe connector and USB 2.0 HS. It is supplied from a single 12V and runs Linux. The FPGA is configured from the processor and also interfaced using PCI Express x1 and a local bus. The system boots from on-board NAND or NOR flash memory.

It is a simple, low-cost measurement device equipped with GPS, GPRS modem, keyboard, display and LiOn battery. It can be also supplied/charged via a USB connector. It is enclosed in a nice-looking Hammond enclosure. It also has 3 RJ50 connectors that enable connection of various types of sensors. Each sensor can be connected using UART, I2C, SPI, 1-wire or analog interface. The device connects with a remote server which is also part of the development. We want to use them at Warsaw University of Technology to build a distributed network of sensors.

A project to host all software and hardware developments related to testing the White Rabbit switch.

A White Rabbit compliant Network Interface Card (NIC) based on the SPEC and the DIO FMC. This project hosts the HDL and associated software to configure the SPEC so it behaves as a NIC under the Linux OS.

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

White Rabbit PTP Core software for LatticeMico32. It consists of a software wrapper for running a PTP daemon without an operating system and device drivers for WRPC HDL internals.

A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.

This project deals with the distribution of RF signals over a White Rabbit network. In particular, it describes ways of extracting the characteristics of an RF signal (I/Q, Amplitude/Phase...) using a WR sampling node and the way to distribute those characteristics through Ethernet frames and generate the RF on the receiving nodes.