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Arria10-based open source timing receiver (PCIe format)

Interface box easing the integration of commercially available (high-voltage) power supplies into a Profibus or Profinet control system. The control system will always see the same API. Implements vendor-specific adaptation (logic, voltage levels).

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

A radiation tolerant flashing beacon design, based on earlier GaN driver developments for radiation tolerant lighting. Currently in the prototype stage with no radiation testing yet performed.

DI/OT Igloo2-based System Board for radiation-exposed DI/OT applications. More info at the Wiki page

Gateware and software for the data acquisition path of the FSI project

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.

The core offers for SoC interconnection:

Master WB interconnection and Slave WB for MSI IRQ.

The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Enumerates the capacitors in an Altium design by parsing the EDIF netlist and library, showing if insufficient voltage ratings are used (derating). More info at the Wiki page

Test. May be deleted.

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page