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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

Collection of WRTD reference designs provided by (and used at) CERN

Idrogen is an Arria10 FPGA board with FMC mezzanine.

PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).

Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.

The core offers for SoC interconnection:

Master WB interconnection and Slave WB for MSI IRQ.

The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

Test. May be deleted.

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.