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A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.
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CompactRIO module with White Rabbit functionality. LabVIEW support, front-panel connector with 10 I/O lines.
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A system to characterize large area silicon pad sensors with several hundred channels. This repository contains the microcontroller firmware.
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VHDL core for absolute position encoders (SSI, BISS, ENDAT).
More info at the Wiki pageUpdated -
Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page
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Projects / FMC High-Voltage supply - fmc-hv-2ch
GNU Lesser General Public License v2.1 onlyFMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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A White Rabbit Timing Receiver in AMC (Advanced Mezzanine Card, AdvancedMC) format. More info at the Wiki page
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Projects / AIDA-2020 TLU - Software
GNU Affero General Public License v3.0Updated -
Projects / AIDA-2020 TLU - Gateware
GNU General Public License v3.0 or laterFPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
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On the Open Hardware Repository you can find projects which use soft-cpu (e.g. mock-turtle, white-rabbit-core, wr-switch). This project offers a toolchain that you can use to compile your code for the soft-cpu target (only LM32 for the time being). The project provides only the necessary makefiles to build the toolchain, so it will be necessary to compile the toolchain.
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A distributed oscilloscope based on the White Rabbit network. More info at the Wiki page
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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Projects / VHDL macro libraries for Microsemi ProASIC3
GNU Affero General Public License v3.0This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.
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