Explore projects
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.
For more information, see the wiki
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Production and functional tests for PandABox.
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Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page
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Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page
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Libre-FDATool is a Python package aimed at helping in the analysis and design of HDL filters from high-level specifications. This Free/Libre Open Source software supports both VHDL and Verilog code generation and relies on a collection of Free scientific and EDA tools for providing advanced features -- simulation, graphics, debugging, etc.
In order to overcome the problems often related with deploying open design toolchains from the ground up across different host environments, Libre-FDATool and the associated third-party tools are alternatively distributed in a customized GNU/Linux virtual machine image. This virtualized solution is ready to use right out of the box and can be easily deployed by only using free software in any mainstream Operating System (GNU/Linux, Windows, OS-X, Solaris).
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. For more details please refer to the wiki pages. Obsolete project. Replaced by VFC-HD.
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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Projects / FMC TDC 1ns 5cha - Software
GNU General Public License v2.0 or laterHost-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.
HW project: https://www.ohwr.org/project/fmc-tdc/wikiUpdated -
Production and functional tests for FMC TDC 1ns 5cha.
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page
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Projects / FMC DEL 1ns 2cha
GNU Lesser General Public License v2.1 onlyA fine delay generator in FMC LPC format with 1 input and 2 outputs. The resolution is 1 ns. Optimized for high frequency pulse repetition rates synchronized to an external clock. More info at the Wiki page
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Production and functional tests for fmc-dac-600m-12b-1cha-dds
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Projects / FMC Bus
GNU General Public License v2.0 or laterThe FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way
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Software to support the FMC ADC 400k 18b 4cha iso mezzanine, including Linux device driver, library and test program.
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Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.
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