Explore projects
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BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page
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Projects / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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SAMD21-based monitoring module for DI/OT power supply and fan tray.
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DI/OT Kintex Ultrascale-based Peripheral Board with HPC FMC and SODIMM DDR4 slot. More info at the Wiki page
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Programmable attenuator of RF signals with very high voltage range (50mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz.
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A project to host all software and hardware developments related to testing the White Rabbit switch.
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This project guides new users to start in the White Rabbit “World” with simple experiments. The starting kit uses two SPEC + FMC-DIO cards. Each node allows basic operations such as input timestamping or programmable output pulse generation. Additionally, specific software and gateware layers allow to use it as a standard network interface card implementing the White Rabbit technology functionalities.
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This project focuses on performing with high precision the core WR PTP calculations in fixed-point arithmetic. This will ensure uniform input parameters, code and precision across all WR implementations.
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Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page
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Projects / Wishbone slave generator
Affero General Public License v1.0wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development - Nice HTML documentation
Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2
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VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page
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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page
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A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page
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Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.
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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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This is a PCB-design + Arduino firmware for an Ethernet-controlled 1:8 RF-multiplexer. It allows selecting as output one of eight input-channels, as commonly used e.g. in timing-laboratories when one wants to measure many RF-sources (clock outputs like 1PPS or 10MHz) with a single instrument (frequency or time-interval counter). The design is for two independent MUX-boards to fit in a 1U 19” rack enclosure. For more information, see the wiki
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.
For more information, see the wiki
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