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A WR compliant Network Interface Core (WR-NIC) for 1G and 10G Ethernet communication. More info at the Wiki page

High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.

For more information, see the wiki

A small PCB that generates 3.3 Volt so that a SVEC can work in older type of VME crates. The SVEC is a VME64x board where usually the 3.3 Volt supply is delivered by the crate itself. Older VME types do not generate this 3.3 Volt.

This open-source 3DMASK offers a FFP2-level protection with the right filter material. It can be produced by anybody in possession of a 3D printer. More info at the Wiki page.

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

VHDL core for absolute position encoders (SSI, BISS, ENDAT).

More info at the Wiki page

This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

fmc-adc-100m14b14cha

For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

More info at the Wiki page

This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

fmc-adc-100m14b14cha

For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

More info at the Wiki page

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

ADC testing procedures and software. More info at the Wiki page

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.

( N.B. Use the sub-project Git repositories, not the top level repository )

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here