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Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

The GBT-based Expandable Front-End (GEFE) is a multipurpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. More info at the Wiki page

The PandABox II Project is a collaboration between ALBA, DESY, DIAMOND, MAXIV, and SOLEIL, to enhance the existing “Position and Acquisition” processing platform called PandABox II. It will provide a New processor Zynq Ultrascale, more configurable I/O, more SFP, and supporting multiple encoder standards (incremental, SSI, BISS...). It will deliver synchronous triggering and data capture capabilities.

EPICS support for Wishbone peripherals: This project consist of a Generic EPICS IOC AsynDriver to support wishbone peripheral. It include the following features:

Driver for X1052, Gennum, Etherbone WB master. Direct access to any register in the wishbone bus Auto-generation of EPICS Database file using wbgen2 Automatic real number convertion (2 complements, fixed point, signess) using .wb file Support for WR Core and other internal bus protocols (i2c, spi, etc.)

More info at the Wiki page

The Furnarius Rufus PCB Milling Machine is an open-source digital fabrication tool designed to lower the costs of prototyping and small scale manufacturing of scientific and educational instruments. More info at the Wiki page

A UV-mask meant for people with a highly sensitive skin. It features 100% protection from UV and has an integrated fan. The design is fully open. More info at the Wiki page

FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB. Project on hold.

ELMB is an analog/digital input/output module with CANbus interface. About 10000 of ELMBs are used in various CERN installations of experiments running on LHC. They are used in control and monitoring of equipment. The ELMB is radiation qualified for an order of around 35 Gy of total intercepted dose.

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page

FMC carrier equipped with a Power PC embedded processor. In addition to the SPEC it has 2 gigabit Ethernet ports, one mini PCIe connector and USB 2.0 HS. It is supplied from a single 12V and runs Linux. The FPGA is configured from the processor and also interfaced using PCI Express x1 and a local bus. The system boots from on-board NAND or NOR flash memory.

WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems. Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for the exchange of data between their sensors and actuators and the control and supervision level. With Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.

CROME (Cern RadiatiOn Monitoring Electronics) is the new read-out electronics for radiation protection at CERN. It performs analog-to-digital conversion of the current signal generated by the radiation detectors (ionization chambers) installed in and outside CERN perimeter providing a continuous real-time measurement of ambient dose equivalent rates. It generates radiation alarms, interlock signals and provides long term permanent and reliable data logging. More info at the Wiki page

TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).

More info at the Wiki page

The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.

E-bone first aims at interfacing an FPGA based PCIe Endpoint core to a collection of other cores. The E-bone release contains a number of general purpose cores within that scope. E-bone specifications cater for both a Control Interconnect and a Fast Transmitter. The Control Interconnect defines a 32 bit wide interconnection between a number of masters and slaves. The Fast Transmitter is a one way path (up to 256 bit wide) aiming at dumping large data sets to the root complex. E-bone is nevertheless not restricted to PCIe interfacing and may be used for developing sub-systems in others environments.

More info at the Wiki page

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

The spec-box-3n allows to use up to three SPEC FMC carriers in stand-alone mode, not plugged inside a PC. An internal 230V supply module powers the SPEC boards. The box contains fans to cool the cards. More info at the Wiki page