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CROME (Cern RadiatiOn Monitoring Electronics) is the new read-out electronics for radiation protection at CERN. It performs analog-to-digital conversion of the current signal generated by the radiation detectors (ionization chambers) installed in and outside CERN perimeter providing a continuous real-time measurement of ambient dose equivalent rates. It generates radiation alarms, interlock signals and provides long term permanent and reliable data logging. More info at the Wiki page

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page

FMC WorldFIP is an interface card for the WorldFIP network in an LPC FMC form-factor. The hardware is described in the FMC WorldFIP project.

FMC MasterFIP is an interface card for the WorldFIP network in an LPC FMC form-factor. More info at the Wiki page

A fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

4-channel 16-bit 250 MS/s (700 MHz analog input bandwidth) ADC (ISLA216P25) FMC module.

We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

A level conversion board in VME64x double-height form factor between TTL and RS485. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics. More info at the Wiki page

The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).

This project develops the metrological capacities required to accelerate the industrial adoption of PTP-WR, through improved hardware and calibration techniques. More info at the Wiki page

WR-HSR is a research project to implement the High-availability Seamless Redundancy (HSR) protocol on White Rabbit switches and dual-port end nodes. The implementation is not part of the roadmap of the White Rabbit project.

Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

ELMB is an analog/digital input/output module with CANbus interface. About 10000 of ELMBs are used in various CERN installations of experiments running on LHC. They are used in control and monitoring of equipment. The ELMB is radiation qualified for an order of around 35 Gy of total intercepted dose.

Cosmic Pi - a low cost distributed cosmic ray detector, based on Raspberry Pi. It makes the detection and analysis of cosmic rays accessible to students, educators and ordinary people. It uses a specially designed detector combined with the low cost hardware of the Raspberry Pi computer for data storage and online analysis. More info at the Wiki page

If you're looking for the V1 prototype schematics and PCB layouts you can find them here Our more recent hardware (V1.5 and V2) plus all code is stored on github and can be found here To learn about the project, have a look at our blog

You can also follow us on Facebook.

The project hardware is currently being developed in EagleCAD but we'll be moving to KiCAD fairly soon.

A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus.

An FMC to test the correct mounting of FMC connectors on FMC carrier boards.

Software to support the FMC ADC 250M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page