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Hardware designs for ROBIN-NP project.

A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer.

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.

( N.B. Use the sub-project Git repositories, not the top level repository )

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.

More information on the wiki page The design is currently used only for the CERN RF-group purposes

Firmware for ROBIN-NP project.

This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.

The documentation is public, and related code is GNU GPL licensed.

A software suite written in Python to help with production tests of PCBs. AKA PTS.

Software support for the SPEC board, including kernel and user-space Linux code. The package also include the fmc-bus driver, which is expected to be used by other carriers as well.

A level conversion board between TTL and 24V blocking levels in VME64x form factor. The project uses a rear transition module for connectivity and a front module with the active conversion and diagnostics electronics. More info at the Wiki page

A project to describe techniques and gather results of the time transfer between CERN and LNGS for the neutrino Time Of Flight experiment.

Software for ROBIN-NP project.

An LPC FMC board which seeks to distribute digital I/O. It is designed to operate at least at 10 MHz, however a better design could allow this board to operate at much higher frequencies. This board is compatible with "PMOD" Connectors.

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus.

A simple 4-lane PXIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Labview driver available for Fine Delay and TDC mezzanines. More info at the Wiki page

A level conversion board in VME64x double-height form factor between TTL and RS485. Direction and levels are configurable. The project uses a Rear Transition Module for connectivity and a Front module with the active conversion and diagnostics electronics. More info at the Wiki page

IPBus is a FPGA Core that controls a Wishbone bus via Ethernet. Currently the transport protocol is UDP/IP, although there are plans for an ATA over Ethernet (AoE) implementation. There are reference designs for the SP601 and SP605 Xilinx FPGA boards.

Details at http://ipbus.web.cern.ch/ipbus/

SPI Boards Package is a set of electronic boards developed at Soleil Synchrotron (France). These boards can be connected together in a daisy chain and they communicate with an embedded controller via an SPI Bus. They provide the following features:

- Platform allowing us to build specific solutions with simple and open tools.

- Modular architecture.

- Provide solutions for applications which require synchronization.

- Low level process implementation to achieve better performance. - Easy Control network connection

The main CPU board contains a microprocessor. It manages a task for communication with the supervision, an embedded process and SPI communication with the peripheral boards. We have a modular approach that means we can make various Peripheral board combinations between 16-bit DAC, 16-bit ADC, and a calculator board for motor encoder.

The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.