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Corelib - Project to share generic HDL cores.

FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB. Project on hold.

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to /-10V or/-5V. The input impedance is 1MOhm.

The nanoFIP test board is used to test the functionality of the nanoFIP design. Apart from the nanoFIP chip, the FielDrive and the FieldTR it houses another Actel FPGA that can access nanoFIP in stand-alone or in memory mode. This FPGA can also communicate through a RS232 port with a windows PC running the NFTC software. The components on the board are placed in such a way that with a focused beam, radiation tests can be performed to the nanoFIP, FielDrive and FieldTR, leaving the rest if the components in a radiation-safe zone. The card has been designed by the company HLP.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

A multi-purpose ARM-based small piggy-back PCB with Linux support, Ethernet, USB, sound, graphic LCD and lots of I/O pins.

Projects not directly identifiable with PCB or HDL core developments.

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

Linux device driver and associated utilities for PCIe FMC carriers. Aka GnuRabbit.

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

GTS is a tool which takes a binary for a given microprocessor (initially an LM32) and gives information about worst-case execution time.

A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.

An FMC for clock & data recovery from optical sources.

A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets

A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.

ADC testing procedures and software. More info at the Wiki page

An FMC to test the correct mounting of FMC connectors on FMC carrier boards.

A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor. More info at the Wiki page

A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page