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This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:
fmc-adc-100m14b14chaFor testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.
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A web based commander based on Node.JS for the HDLMake tool.
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EDM is a Embedded Design Module standard under the Creative Commons license targeting on embedded applications and controllers which are being actively developed by many embedded companies. See http://www.edm-standard.org. This projects holds all EDM compatible boards.
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.
The core offers for SoC interconnection:
Master WB interconnection and Slave WB for MSI IRQ.The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page
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The dual channel L band front-end consist of a FMC dual channel L band down-converter, preamplifiers and duplex filters. Each IQ down-converter has a wide adjustable bandwidth (>100 MHz), adjustable gain and two 250MHz 8 bits or 160 MHZ 12 bits or 105MHZ 14 bits multi-mode ADC's. The down-converter mode is switchable: single receiving frequency band for both channels, or dual frequency band: each channel has its own receiving frequency band. For GNSS its includes timing support, Other applications are radio astronomy and microwave digitizing back-end.
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This project presents an FPGA architecture for the computation of visual attention based on the combination of a bottom-up saliency and a top-down task-dependent modulation streams. The bottom-up stream is deployed including optical flow, local energy, red-green and blue-yellow color opponencies, and different local orientation maps. The final saliency is modulated by two highlevel features: optical flow and disparity. The architecture include some feedback masks to adapt the weights of the features that are part of the bottom-up stream, depending on the specific target application. The target applications are ADAS (Advanced Driving Assistance Systems), video surveillance, robotics, etc...
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DI/OT Igloo2-based System Board for radiation-exposed DI/OT applications. More info at the Wiki page
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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Couples a MAROC ASIC (64 channels each with a fixed threshold discriminator and a slow shaper + sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet (firmware supplied supports IPBus). Multiple boards can be plugged together to increase the channel count. Clocking circuitry compatible with the White Rabbit implementation of PTP. More info at the Wiki page
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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The programmable bench power supply project was an attempt to create reliable, modular, open and programmable power supply. Various voltage single range operation (i.e. 0 – 30 V, 0 – 40 V or 0 – 50 V per channel). Various current single range operation (i.e. 0 – 3 A or 0 – 5 A per channel)
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
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A system to characterize large area silicon pad sensors with several hundred channels. This repository contains the microcontroller firmware.
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Hardware and software (libraries and GUI) to implement the SFF-8472 standard “Diagnostic Monitoring Interface for Optical Transceivers”. The hardware implements four SFP+s that can be exercised in parallel. To access the I2C interfaces a USB to I2C chip is used. More info at the Wiki page
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USB-controlled data acquisition and instrument controller, 4 analog inputs, 2 analog outputs, 4 digital inputs and 4 digital outputs. Maximum sampling rate of 3000 samples per seconds in continuous stream mode. On-board averaging at 50000 samples per seconds max. Available in 3 versions:
BNC connectors Terminal Block connections OEM HeaderUpdated -
Projects / FMC DEL 1ns 4cha - stand-alone application
GNU General Public License v3.0 onlyA fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page
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WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems. Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for the exchange of data between their sensors and actuators and the control and supervision level. With Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.
The insourcing project has started with , a rad-tol FPGA that acts as an agent in the communication over the WorldFIP fieldbus.
nanoFIP project details, specifications, design and users information
In view of reorganizing the project, the nanoFIP project contains a copy of the CERNFIP wiki pages, Documents and Issues made on 24 March 2015
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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