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A project devoted to developing and discussing the CERN Open Hardware Licence. More info at the Wiki page

White Rabbit is a fully deterministic Ethernet-based network for general purpose data transfer and synchronization. It can synchronize over 1000 nodes with sub-ns accuracy over fiber lengths of up to 10 km. Commercially available. More info at the Wiki page

SAMD21-based monitoring module for DI/OT power supply and fan tray.

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support

Common gateware for the different level conversion circuits.

Production and functional tests for Conv TTL Blocking. More info at the Wiki page

This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.

The documentation is public, and related code is GNU GPL licensed.

SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page

This project covers all efforts geared to standardize White Rabbit, with a view to providing a stable specification which everyone can use to build compliant products.

FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU

Uses "IPBus Build" ( ipbb )

Build instructions at Instructions here

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

Production and functional tests for Conv TTL RS485

A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.

( N.B. Use the sub-project Git repositories, not the top level repository )