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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page

A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page

Gateware (HDL design) for MasterFIP.

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

Gateware (HDL design) for Conv TTL RS485

Corelib - Project to share generic HDL cores.

This project contains all the HDL gateware necessary for the FPGA of the WR switch.

The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.