scrips: removal of adc-related folder and renamed pts_log folder to masterfip_log

Added firmware supporting watchdog test.
Last register update (just in case).

Allowed flattened stucture in FPGA design in order to help routing.

Included binary was build with previous commit.

Output binary not included!!!!
Removed one of CPU cores from mockturtle.
Fixed path bug in pts/fmcmasterfip.py
Update csr interfaces for updated gw-masterfip.

Added flush to tests in order to remove empty log files.
Small message fix in test02.

Changed ext_sync termination_en pin (previously used by ext_sync_test).
Error messages fixed in test06.

Cleaned some scripts.

Watchdog test require changes is fmcmasterfip_core.
Small modification in test01 preventing unwanted blink of diodes.

Added masterfip_pts core to top module.
Modified and verified test06 to match gateware changes.
Changed sync input to inout on top module.

Verified communication on bus (first sutest of test02)

Synthesized.
i2c, main csr and mf_pts_csr must be added

Added masterfip-gw submodule.
Updated other submodules to work with masterfip-gw.
Generated csr files for new masterfip_core.
Updated ise project.
Verified implementation of spec_masterfip_pts.

Stopped inserting adc modules

Removed outdated file.