Added watchdog test script (for debugging)

python/test_wdg.py

+#!   /usr/bin/env   python
+
+# Copyright Creotech SA, 2016
+# Author: Marek Guminski <marek.guminski@creotech.pl>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+
+import spec
+import fmcmasterfip as fmc
+import utilities as util
+import time
+import ptsexcept
+from time import sleep
+from spec_identification import dut_bus
+import sys
+
+
+PLOT=True
+
+
+       
+def main (card=None, default_directory='.',suite=None,serial=""):
+    
+        
+    ###############################################################################
+    ############################ initialization ###################################
+    ###############################################################################
+    util.section_msg("Hardware initialization")
+    abspath = util.find_prj_topdir(util.TOPDIRNAME);
+    carrier = spec.spec( abspath );
+        
+    # FPGA bitstream and FMC presence are verified during initialization
+    dut = fmc.fmcmasterfip(carrier, abspath, util.FIRMWARE_PATH)
+    
+    dut.rst_core()
+    dut.rst_fd()
+
+    while(1):
+        dut.send_id_dat(0x7F14, int( sys.argv[1], 16 ) )
+        time.sleep(0.1)
+        
+if __name__ == '__main__' :
+    main()
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