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wr-switch-hdl
Commit f3c3994c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wrsw_swcore: added cross-hierarchy chipscope probes

parent 2cf7a47b
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Showing with 113 additions and 34 deletions
modules/wrsw_swcore/Manifest.py
View file @ f3c3994c
......@@ -9,7 +9,6 @@
files = [
"swc_swcore_pkg.vhd",
"swc_block_alloc.vhd",
"swc_core.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
......@@ -18,7 +17,7 @@ files = [
#"swc_packet_mem.vhd",
#"swc_packet_mem_read_pump.vhd",
#"swc_packet_mem_write_pump.vhd",
"swc_page_alloc.vhd",
#"swc_page_alloc.vhd",
"swc_page_alloc_old.vhd",
"swc_pck_pg_free_module.vhd",
"swc_pck_transfer_arbiter.vhd",
......
modules/wrsw_swcore/swc_multiport_page_allocator.vhd
View file @ f3c3994c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2012-02-02
-- Last update: 2012-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -81,7 +81,8 @@ entity swc_multiport_page_allocator is
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic
nomem_o : out std_logic;
tap_out_o : out std_logic_vector(62 + 49 downto 0)
);
end swc_multiport_page_allocator;
......@@ -165,6 +166,15 @@ architecture syn of swc_multiport_page_allocator is
-- signal set_usecnt_done : std_logic_vector(g_num_ports-1 downto 0);
signal pg_free_last_usecnt : std_logic;
function f_slv_resize(x : std_logic_vector; len : natural) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
tmp := (others => '0');
tmp(x'length-1 downto 0) := x;
return tmp;
end f_slv_resize;
begin -- syn
......@@ -322,5 +332,29 @@ begin -- syn
set_usecnt_done_o <= set_usecnt_done_feedback;--set_usecnt_done;
force_free_done_o <= force_free_done;
nomem_o <= pg_nomem;
tap_out_o <= f_slv_resize
(
alloc_i &
free_i &
force_free_i &
set_usecnt_i &
alloc_done&
free_done &
force_free_done& -- 56
set_usecnt_done_feedback & -- 48
pg_alloc & -- 47
pg_free & -- 46
pg_free_last_usecnt & -- 45
pg_force_free & -- 44
pg_set_usecnt & -- 43
pg_usecnt & -- 40
pg_addr & -- 30
pg_addr_alloc & -- 20
pg_done & -- 19
pg_nomem & -- 18
'0' & -- 17
'0', -- 16
50 + 62);
end syn;
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ f3c3994c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2012-03-12
-- Last update: 2012-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -70,27 +70,28 @@ package swc_swcore_pkg is
zero_o : out std_logic);
end component;
component swc_page_allocator
generic (
g_num_pages : integer;
g_num_pages : integer;
g_page_addr_width : integer;
g_num_ports : integer ;
g_usecount_width : integer);
g_num_ports : integer;
g_usecount_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
alloc_i : in std_logic;
free_i : in std_logic;
force_free_i : in std_logic;
set_usecnt_i : in std_logic;
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
alloc_i : in std_logic;
free_i : in std_logic;
force_free_i : in std_logic;
set_usecnt_i : in std_logic;
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
free_last_usecnt_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
idle_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
end component;
--component swc_page_allocator
......@@ -110,8 +111,6 @@ package swc_swcore_pkg is
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
free_last_usecnt_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
......@@ -137,7 +136,7 @@ package swc_swcore_pkg is
g_page_num : integer; --:= c_swc_packet_mem_num_pages
g_size_width : integer ;
g_partial_select_width : integer ;
g_data_width : integer
g_data_width : integer
);
port (
rst_n_i : in std_logic;
......@@ -221,7 +220,9 @@ package swc_swcore_pkg is
pta_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
pta_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0)
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
tap_out_o : out std_logic_vector(49+62 downto 0)
);
end component;
......@@ -250,7 +251,8 @@ package swc_swcore_pkg is
usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic
nomem_o : out std_logic;
tap_out_o :out std_logic_vector(62 + 49 downto 0)
);
end component;
......@@ -389,7 +391,9 @@ package swc_swcore_pkg is
ppfm_free_done_i : in std_logic;
ppfm_free_pgaddr_o : out std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out
src_o : out t_wrf_source_out;
tap_out_o : out std_logic_vector(15 downto 0)
);
end component;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ f3c3994c
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-29
-- Last update: 2012-03-12
-- Last update: 2012-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -266,10 +266,48 @@ architecture rtl of xswc_core is
signal mmu2ppfm_free_last_usecnt : std_logic_vector(g_num_ports-1 downto 0);
---- end tmp
begin --rtl
type t_tap_ib_array is array(0 to g_num_ports-1) of std_logic_vector(49+62 downto 0);
type t_tap_ob_array is array(0 to g_num_ports-1) of std_logic_vector(15 downto 0);
signal tap_mpm : std_logic_vector(61 downto 0);
signal tap_ib : t_tap_ib_array;
signal tap_ob : t_tap_ob_array;
signal tap_alloc : std_logic_vector(62 + 49 downto 0);
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal CONTROL0 : std_logic_vector(35 downto 0);
signal tap : std_logic_vector(127 downto 0);
begin --rtl
--chipscope_icon_1: chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--chipscope_ila_1: chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_i,
-- TRIG0 => tap(31 downto 0),
-- TRIG1 => tap(63 downto 32),
-- TRIG2 => tap(95 downto 64),
-- TRIG3 => tap(127 downto 96));
tap <= tap_alloc & tap_ob(2);
gen_blocks : for i in 0 to g_num_ports-1 generate
INPUT_BLOCK : xswc_input_block
......@@ -359,8 +397,9 @@ architecture rtl of xswc_core is
pta_pageaddr_o => ib_pageaddr_to_pta((i + 1) * c_mpm_page_addr_width-1 downto i * c_mpm_page_addr_width),
pta_mask_o => ib_mask ((i + 1) * g_num_ports -1 downto i * g_num_ports),
pta_prio_o => ib_prio ((i + 1) * c_prio_width -1 downto i * c_prio_width),
pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width)
pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
tap_out_o => tap_ib(i)
);
......@@ -418,7 +457,9 @@ architecture rtl of xswc_core is
-------------------------------------------------------------------------------
src_i => src_i(i),
src_o => src_o(i)
src_o => src_o(i),
tap_out_o => tap_ob(i)
);
end generate gen_blocks;
......@@ -528,7 +569,8 @@ architecture rtl of xswc_core is
pgaddr_force_free_i => ppfm_force_free_pgaddr,
nomem_o => mmu_nomem
nomem_o => mmu_nomem,
tap_out_o => tap_alloc
);
MULTIPORT_MEMORY: mpm_top --(new)
......
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