modules/wrsw_swcore/mpm: mpm_async_fifo: added extra gray counter sync stage to…

modules/wrsw_swcore/mpm: mpm_async_fifo: added extra gray counter sync stage to prevent (rather improbable) metastability

modules/wrsw_swcore/mpm: mpm_async_fifo: added extra gray counter sync stage to…
modules/wrsw_swcore/mpm: mpm_async_fifo: added extra gray counter sync stage to prevent (rather improbable) metastability
2cf7a47b · Tomasz Wlostowski · 97e035f9 · 2cf7a47b
Commit 2cf7a47b authored Mar 16, 2012 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 6 additions and 3 deletions

mpm_async_fifo_ctrl.vhd modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd +6 -3

No files found.
--- a/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
@@ -92,7 +92,7 @@ architecture rtl of mpm_async_fifo_ctrl is

  type t_counter_block is record
    bin, bin_next, gray, gray_next : t_counter;
-    bin_x, gray_x                  : t_counter;
+    bin_x, gray_x, gray_xm                       : t_counter;
  end record;


@@ -137,14 +137,17 @@ begin  -- rtl
  p_sync_read_ptr : process(clk_wr_i)
  begin
    if rising_edge(clk_wr_i) then
-      rcb.gray_x <= rcb.gray;
+      rcb.gray_xm <= rcb.gray;
+      rcb.gray_x <= rcb.gray_xm;
    end if;
  end process;

+ 
  p_sync_write_ptr : process(clk_rd_i)
  begin
    if rising_edge(clk_rd_i) then
-      wcb.gray_x <= wcb.gray;
+      wcb.gray_xm <= wcb.gray;
+      wcb.gray_x <= wcb.gray_xm;
    end if;
  end process;