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wr-nic
Commit 675112d3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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updated xwb_crossbar component instances inside dio core and top module

parent 2e641787
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Showing with 13 additions and 17 deletions
modules/wrsw_dio/wrsw_dio.vhd
View file @ 675112d3
...@@ -491,7 +491,10 @@ begin ...@@ -491,7 +491,10 @@ begin
generic map( generic map(
g_num_masters => 1, g_num_masters => 1,
g_num_slaves => 4, g_num_slaves => 4,
g_registered => true g_registered => true,
-- Address of the slaves connected
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask
) )
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
...@@ -501,10 +504,7 @@ begin ...@@ -501,10 +504,7 @@ begin
slave_o(0) => slave_o, slave_o(0) => slave_o,
-- Slave conenctions -- Slave conenctions
master_i => cbar_master_in, master_i => cbar_master_in,
master_o => cbar_master_out, master_o => cbar_master_out
-- Address of the slaves connected
cfg_address_i => c_cfg_base_addr,
cfg_mask_i => c_cfg_base_mask
); );
gen_pio_assignment: for i in 0 to 4 generate gen_pio_assignment: for i in 0 to 4 generate
......
top/spec/wr_nic_top.vhd
View file @ 675112d3
...@@ -425,19 +425,16 @@ architecture rtl of wr_nic_top is ...@@ -425,19 +425,16 @@ architecture rtl of wr_nic_top is
generic( generic(
g_num_masters : integer; g_num_masters : integer;
g_num_slaves : integer; g_num_slaves : integer;
g_registered : boolean g_registered : boolean;
); g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0); slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0); slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0); master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0); master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
-- Address of the slaves connected
cfg_address_i : in t_wishbone_address_array(g_num_slaves-1 downto 0);
cfg_mask_i : in t_wishbone_address_array(g_num_slaves-1 downto 0)
);
end component; end component;
-- IRQ Gen -- IRQ Gen
...@@ -801,7 +798,9 @@ begin ...@@ -801,7 +798,9 @@ begin
generic map( generic map(
g_num_masters => 1, g_num_masters => 1,
g_num_slaves => 5, g_num_slaves => 5,
g_registered => true g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask
) )
port map( port map(
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
...@@ -811,10 +810,7 @@ begin ...@@ -811,10 +810,7 @@ begin
slave_o(0) => cbar_slave_o, slave_o(0) => cbar_slave_o,
-- Slave conenctions -- Slave conenctions
master_i => cbar_master_i, master_i => cbar_master_i,
master_o => cbar_master_o, master_o => cbar_master_o
-- Address of the slaves connected
cfg_address_i => c_cfg_base_addr,
cfg_mask_i => c_cfg_base_mask
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
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