Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
wr-nic
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
white-rabbit
wr-nic
Commits
675112d3
Commit
675112d3
authored
Jun 07, 2012
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
updated xwb_crossbar component instances inside dio core and top module
parent
2e641787
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
13 additions
and
17 deletions
+13
-17
wrsw_dio.vhd
modules/wrsw_dio/wrsw_dio.vhd
+5
-5
wr_nic_top.vhd
top/spec/wr_nic_top.vhd
+8
-12
No files found.
modules/wrsw_dio/wrsw_dio.vhd
View file @
675112d3
...
...
@@ -491,7 +491,10 @@ begin
generic
map
(
g_num_masters
=>
1
,
g_num_slaves
=>
4
,
g_registered
=>
true
g_registered
=>
true
,
-- Address of the slaves connected
g_address
=>
c_cfg_base_addr
,
g_mask
=>
c_cfg_base_mask
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
...
...
@@ -501,10 +504,7 @@ begin
slave_o
(
0
)
=>
slave_o
,
-- Slave conenctions
master_i
=>
cbar_master_in
,
master_o
=>
cbar_master_out
,
-- Address of the slaves connected
cfg_address_i
=>
c_cfg_base_addr
,
cfg_mask_i
=>
c_cfg_base_mask
master_o
=>
cbar_master_out
);
gen_pio_assignment
:
for
i
in
0
to
4
generate
...
...
top/spec/wr_nic_top.vhd
View file @
675112d3
...
...
@@ -425,19 +425,16 @@ architecture rtl of wr_nic_top is
generic
(
g_num_masters
:
integer
;
g_num_slaves
:
integer
;
g_registered
:
boolean
);
g_registered
:
boolean
;
g_address
:
t_wishbone_address_array
;
g_mask
:
t_wishbone_address_array
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in_array
(
g_num_masters
-1
downto
0
);
slave_o
:
out
t_wishbone_slave_out_array
(
g_num_masters
-1
downto
0
);
master_i
:
in
t_wishbone_master_in_array
(
g_num_slaves
-1
downto
0
);
master_o
:
out
t_wishbone_master_out_array
(
g_num_slaves
-1
downto
0
);
-- Address of the slaves connected
cfg_address_i
:
in
t_wishbone_address_array
(
g_num_slaves
-1
downto
0
);
cfg_mask_i
:
in
t_wishbone_address_array
(
g_num_slaves
-1
downto
0
)
);
master_o
:
out
t_wishbone_master_out_array
(
g_num_slaves
-1
downto
0
));
end
component
;
-- IRQ Gen
...
...
@@ -801,7 +798,9 @@ begin
generic
map
(
g_num_masters
=>
1
,
g_num_slaves
=>
5
,
g_registered
=>
true
g_registered
=>
true
,
g_address
=>
c_cfg_base_addr
,
g_mask
=>
c_cfg_base_mask
)
port
map
(
clk_sys_i
=>
clk_sys
,
...
...
@@ -811,10 +810,7 @@ begin
slave_o
(
0
)
=>
cbar_slave_o
,
-- Slave conenctions
master_i
=>
cbar_master_i
,
master_o
=>
cbar_master_o
,
-- Address of the slaves connected
cfg_address_i
=>
c_cfg_base_addr
,
cfg_mask_i
=>
c_cfg_base_mask
master_o
=>
cbar_master_o
);
------------------------------------------------------------------------------
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment