The uRV core

Project description

The uRV (Micro RISC-V) is a small footprint 32-bit RISC-V processor core intended for embedded real-time applications. uRV is targeted primarily for use as a soft CPU core in FPGAs.

Features

• Supports RV32IM instruction set. Division and multiply high instructions are optional and can be emulated to lower the FPGA footprint.
• Target: FPGAs.
• 4-stage pipeline (FDXW).
• All instructions except taken branches/division in one clock cycle.
• Code execution from internal memory block.
• Wishbone bus (version B.4) for peripheral access.
• Simple interrupt handling.
• Verilog RTL code.

Under development:

• JTAG/Debug unit.
• Compressed ISA (RV32IMC) extension as it matures.
• Caches (Wishbone B.4 and AXI4 memory I/F).

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Project information

• Developing Distributed Hard-Real Time Software Systems Using FPGAs and Soft Cores, T. Wlostowski et al., 2016
• Users

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Contacts

• Tomasz Włostowski (CERN)

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Status

Date	Event
19-05-2015	First version.
06-08-2015	CoreMark® works.
09-11-2021	Project being used internally at CERN. Not yet ready to be offered as a block. A new version may include support for the RISC-V compressed instructions, which result in smaller binaries for the firmware.

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9 November 2021

Files

• logo.png