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White Rabbit Trigger Distribution
Commit f39decae authored by Tristan Gingold's avatar Tristan Gingold
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fd_x2: fix aux clock handling in hdl

parent 737c1593
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Showing with 9 additions and 10 deletions
hdl/top/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.vhd
View file @ f39decae
......@@ -48,8 +48,7 @@ use unisim.vcomponents.all;
entity wrtd_ref_svec_fd_x2 is
generic (
g_WRPC_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../software/firmware/fd/wrtd-rt-fd.bram";
g_MT_CPU0_INITF : string := "../../../software/firmware/fd-x2/wrtd-rt-fd-x2.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
......@@ -331,14 +330,14 @@ architecture arch of wrtd_ref_svec_fd_x2 is
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ext_ref : std_logic;
signal tdc_clk_125m : std_logic;
signal clk_dmtd_125m : std_logic;
signal dcm1_clk_ref_0 : std_logic;
signal dcm1_clk_ref_180 : std_logic;
signal dcm0_clk_ref_0 : std_logic;
signal dcm0_clk_ref_180 : std_logic;
attribute keep : string;
attribute keep of tdc_clk_125m : signal is "TRUE";
attribute keep of dcm0_clk_ref_0 : signal is "TRUE";
attribute keep of dcm1_clk_ref_0 : signal is "TRUE";
signal vme_access_led : std_logic;
......@@ -463,7 +462,7 @@ begin -- architecture arch
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => tdc_clk_125m,
clk_aux_i(0) => dcm0_clk_ref_0,
clk_aux_i(1) => dcm1_clk_ref_0,
clk_10m_ext_i => clk_ext_ref,
pps_ext_i => pps_ext_in,
......@@ -525,6 +524,7 @@ begin -- architecture arch
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
pcbrev_i => pcbrev_i,
clk_dmtd_125m_o => clk_dmtd_125m,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
......@@ -603,7 +603,6 @@ begin -- architecture arch
generic map (
g_CONFIG => c_MT_CONFIG,
g_CPU0_IRAM_INITF => g_MT_CPU0_INITF,
g_CPU1_IRAM_INITF => g_MT_CPU1_INITF,
g_WITH_WHITE_RABBIT => TRUE)
port map (
clk_i => clk_sys_62m5,
......@@ -694,7 +693,7 @@ begin -- architecture arch
inst_FineDelay_Core0 : entity work.fine_delay_core
generic map (
g_FMC_SLOT_ID => 1,
g_FMC_SLOT_ID => 0,
g_WITH_WR_CORE => TRUE,
g_SIMULATION => f_int2bool(g_SIMULATION),
g_INTERFACE_MODE => PIPELINED,
......@@ -703,7 +702,7 @@ begin -- architecture arch
clk_ref_0_i => dcm0_clk_ref_0,
clk_ref_180_i => dcm0_clk_ref_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
clk_dmtd_i => clk_dmtd_125m,
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr0_pll_locked,
......@@ -797,7 +796,7 @@ begin -- architecture arch
ddr1_pll_reset <= not fmc1_fd_pll_status_i;
fmc1_fd_pll_status <= fmc1_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core : entity work.fine_delay_core
inst_FineDelay_Core1 : entity work.fine_delay_core
generic map (
g_FMC_SLOT_ID => 1,
g_WITH_WR_CORE => TRUE,
......@@ -808,7 +807,7 @@ begin -- architecture arch
clk_ref_0_i => dcm1_clk_ref_0,
clk_ref_180_i => dcm1_clk_ref_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
clk_dmtd_i => clk_dmtd_125m,
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr1_pll_locked,
......
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