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White Rabbit Trigger Distribution
Commit 737c1593 authored by Tristan Gingold's avatar Tristan Gingold
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Add fd_x2 design

parent ffb33262
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hdl/syn/wrtd_ref_svec_fd_x2/Manifest.py 0 → 100644
View file @ 737c1593
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_fd_x2"
syn_project = "wrtd_ref_svec_fd_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_svec_fd_x2.ucf",
"buildinfo_pkg.vhd",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd0.ucf",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd1.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_fd_x2",
],
}
#syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_fd_x2/syn_extra_steps.tcl 0 → 100644
View file @ 737c1593
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.ucf 0 → 100644
View file @ 737c1593
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
# Exceptions for crossings via gc_sync_ffs
#TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_ffs = FROM fdl_clk TO "fdl_sync_ffs" TIG;
#TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_reg = FROM fdl_clk TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
hdl/top/wrtd_ref_svec_fd_x2/Manifest.py 0 → 100644
View file @ 737c1593
files = [
"wrtd_ref_svec_fd_x2.vhd",
"wrtd_fd_x2_host_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/wrtd_ref_svec_fd_x2/wrtd_fd_x2_host_map.cheby 0 → 100644
View file @ 737c1593
memory-map:
name: wrtd_fd_x2_host_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fd
description: FD
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
description: Mock Turtle
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_fd_x2/wrtd_fd_x2_host_map.vhd 0 → 100644
View file @ 737c1593
-- Do not edit. Generated on Tue Feb 23 14:50:12 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl -i wrtd_fd_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_fd_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the carrier metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FD
fd_i : in t_wishbone_master_in;
fd_o : out t_wishbone_master_out;
-- Mock Turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_fd_x2_host_map;
architecture syn of wrtd_fd_x2_host_map is
signal adr_int : std_logic_vector(18 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fd_re : std_logic;
signal fd_we : std_logic;
signal fd_wt : std_logic;
signal fd_rt : std_logic;
signal fd_tr : std_logic;
signal fd_wack : std_logic;
signal fd_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(18 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(18 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface fd
fd_tr <= fd_wt or fd_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fd_rt <= '0';
fd_wt <= '0';
else
fd_rt <= (fd_rt or fd_re) and not fd_rack;
fd_wt <= (fd_wt or fd_we) and not fd_wack;
end if;
end if;
end process;
fd_o.cyc <= fd_tr;
fd_o.stb <= fd_tr;
fd_wack <= fd_i.ack and fd_wt;
fd_rack <= fd_i.ack and fd_rt;
fd_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
fd_o.sel <= wr_sel_d0;
fd_o.we <= fd_wt;
fd_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, metadata_wack, fd_wack, mt_wack) begin
metadata_we <= '0';
fd_we <= '0';
mt_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
case wr_adr_d0(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "1" =>
-- Submap fd
fd_we <= wr_req_d0;
wr_ack_int <= fd_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "01" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_int <= mt_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, fd_i.dat, fd_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
fd_re <= '0';
mt_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
case adr_int(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "1" =>
-- Submap fd
fd_re <= rd_req_int;
rd_dat_d0 <= fd_i.dat;
rd_ack_d0 <= fd_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "01" =>
-- Submap mt
mt_re <= rd_req_int;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/top/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.vhd 0 → 100644
View file @ 737c1593
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